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Politics : Formerly About Advanced Micro Devices
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To: Ali Chen who wrote (23561)9/27/1997 1:46:00 PM
From: Elmer   of 1571724
 
Ali wrote:
<When the P6 processor issues a memory access transaction, and that memory location is cached, the memory access transaction to the system is simply aborted>. When any CPU "issues a memory access transaction, and that memory location is cached", and the cacheline is not marked as "modified", THE MEMORY ACCESS TRANSACTION JUST NEVER HAPPENED! This is by definition of any reasonable cache controller!

Great Ali, you grasp some caching comcepts, but this is not what we
were discussing. You have jumped in to the middle of something
without knowing what started the discussion. The point in question
is not WHAT happens (you are in violent agreement with me there)
but WHERE it happens.

Repeat:
The processor controls the cache, the processor controls the cache.

You jumped into this late and I'm not going to vector off on a dead
end arguement with you.

EP
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