Sigh. More insulting rants. Can't you argue without personal attacks? All this "calm down", "madeup imaginary[sic]", "looking for reds under the bed which ain't there" stuff is just so not needed.
Let's edit your post, and remove all that unnecessary junk, and see what is left:
(1) Of course the 8-series is where it should be released first as not only are they the most lucrative priced AMD products but it will allow 16 and 32 K8L core systems which will encroach further on high-end Unix systems and keep the 8 series asp high.
(2) The die is ~286 sq mm btw as measured by semico professionals and is not a surprise to anyone least alone AMD.
(3) AMD did not promise you or anybody any benches or clock numbers
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To point (1), I think you are ignoring the sheer number of 2S systems that are sold. How much demand is there for >8 core systems vs. 8 and below? I maintain the order of introduction follows from ramp economics, particularly with a relatively low-yielding product, and not any special benefit (other than small size and high asp) to 4S systems. Ignoring the competitive angle is also odd. AMD is doing relatively okay in 4S. It's the <4S area where they need the most reinforcement.
To point (2), are you saying there is an official estimate that has been released by someone with access to the Barcelona samples? To my knowledge, there has been an estimate based on wafer count (via pgerassi), some work based on a die plot by Hans and others, and now, we have a photograph of the part mounted on a substrate of known size. That should provide a rather good estimate, which is what I attempted to do.
Also to point (2), I don't believe anyone is claiming AMD is particularly surprised by the die size, unless that turns out to be process-health related and we should know more about that when the Rev G die size is released. Surprised or not, a ~300mm^2 die is going to be challenging to yield, especially with the core areas appearing to be a large fraction of the die area (vs. cache, not as sensitive to defects due to built in redundancy).
To point (3), AMD did promise to talk more about performance and power, and my inference was that for such talk to be at all meaningful, it would need to be *real data* this time, and not just simulated projections. I don't think this is a far-fetched notion.
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How about a courteous reply this time? |
