ISSCC Monday, February 12th
5.4 An Integrated Quad-Core OpteronTM Processor 3:15 PM
J. Dorsey1, S. Searles1, M. Ciraula1, E. Fang2, S. Johnson1, N. Bujanos1, R. Kumar2,
D. Wu1, M. Braganza1, S. Meyers1
AMD
An integrated quad-core x86 processor is implemented in a 65nm 11M SOI CMOS
process. Based on an enhanced OpteronTM core, the SoC-developed processor employs
power- and thermal-management techniques throughout the design. The SRAM cache
designs target process variation considerations and future process scalability. A
DDR2/DDR3 combo-PHY and HT3 I/Os provide high-bandwidth interfaces.
5.6 Implementation of the 65nm Dual-Core 64b Merom Processor 4:15 PM,
N. Sakran, M. Yuffe, M. Mehalel, J. Doweck, E. Knoll, A. Kovacs
Intel, Haifa, Israel
Merom is a dual-core 64b processor implementing the CoreTM architecture. The 143mm2
die has 291M transistors in a 65nm 8M process. The shared 4MB 16-way L2 cache
uses PMOS power gating to minimize leakage. The processor operates in a wide core
frequency range of 1 to 3GHz, a bus frequency range of 666 to 1333MHz and voltage
range of 0.85 to 1.325V, while providing 40% better power performance.
Regards, Hans |
