"Your stance has been noted"
I have told ephud several times in the past years that there is a _known_ problem with bin splits, that below 0.1um all transistors become "fuzzy", their parameters are subject to _continuous_ spectrum, they cannot be considered as having same parameters across individual chip. As result, faulty (functional but underperforming) signal path could be anywhere in the chip, and several of them, so the concept of "critical path" is no longer a good indication of where to improve chip timing. It is a known problem to academia, I've seen papers on this subject since 2001 I believe (and no, I am not going to dig references for ephud).
Ephud first tried to ridicule me (how silly), tried to impress public with old idea of "stuck_at_fault" testing, but then indirectly admitted that he has heard about the problem of "intra-chip" variance.
I believe this is a typical lag between academia and some industrial engineers. Many narrowly educated engineers and their managers have little capability to grasp emerging concepts that differ drastically from what they have been trained on, hence the result, first denial, then long learning curve. I believe the industry took first hit of this problem during "1 million Coppermines per week" ordeal. I think Intel posters confused the amount of functional dies at wafer test with final bin distribution. Ephud still denies this, I guess. I think there is no need to hide behind any NDA or any other excuses, it is a well-known issue.
Hope you are doing well in exile,
Cheers,
- Ali |
