"It appears he's implying that yield numbers don't reflect the effects of intra-die variation as well as inter-die variation. Note the terms intra and inter. The only way that could happen is if you couldn't determine the intra and inter die variation. That's just not the case. You certainly can. So while yield numbers don't tell you the actual binsplit information in a single number, they still reflect the number of saleable die, or at least to a very high probability."
It is amazing how hard is to communicate even simplest things. I am sure I said many times that I am talking about "sellable dies", while you again and again misspell it as "sealble die" :-). Sealable != sellable. Combjelly also told you this.
Someone on this thread was bragging about how wonderfully overclockable the current Intel processors are. Yet they are still selling 1.6 GHz chips while amateurs can overclock certain samples to what? 5 HGz? Actually, I don't care much whether do you find ways to downbin dies at wafer sort, or after packaging. The fact remains that the clock of finished sub-100nm chips is severely handicapped, and indications are that it is due to ever growing variability of individual transistors within the same die. In other words, yield numbers are made up by shifting to frequencies about 1/3 of chip potential, by binning dies into half-cache chips, into half-fsb chips, and crippled Celerons. The point I was trying to make in my original remark is that there is no need to pretend that you know much more, that you are under some NDA, etc, and hide behind vague scary phrases about "revealing issues that reveals something that reveals itself...". It is a known problem, with factual support. That's it.
- Ali |
