edit: I need a reference on the 2004 IEDM paper with the Intel data. I just scanned through them and couldn't find an author from Intel publishing on the 45 nm node.
edit: Here are the citations and abstracts that I see:
1. Future semiconductor manufacturing: challenges and opportunities
Iwai, H.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
13-15 Dec. 2004
Page(s): 11- 16
Digital Object Identifier 10.1109/IEDM.2004.1419051
Summary: Recently, CMOS scaling has been accelerated very aggressively in both production and research levels. Already, sub-100 nm gate length CMOS LSIs are used for many applications in a huge volume and even transistor operation of 5 nm gate length CMOS wa.....
AbstractPlus | Full Text: PDF IEEE CNF
2. Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devices
Severi, S.; Anil, K.G.; Henson, K.; Lauwers, A.; Veloso, A.; de Marneffe, J.F.; Ramos, J.; Eyben, P.; Vandervost, W.; Jurczak, M.; Biesemans, S.; De Meyer, K.; Pawlak, J.B.; Duffy, R.; Lindsay, R.; Camillo-Castillo, R.A.; Dachs, C.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
13-15 Dec. 2004
Page(s): 99- 102
Digital Object Identifier 10.1109/IEDM.2004.1419076
Summary: This paper reports on the successful integration of truly diffusion-less (less-than-650/spl deg/C) junction formation by SPER in pMOSFETs in combination with Ni-FUSI gates for the first time. The obtained drive currents are 355 /spl mu/A//spl mu/m f.....
AbstractPlus | Full Text: PDF IEEE CNF
3. Impact of parasitic resistance and silicon layer thickness scaling for strained-silicon MOSFETs on relaxed Si/sub 1-x/Ge/sub x/ virtual substrate
Kawasaki, H.; Ohuchi, K.; Oishi, A.; Fujii, O.; Tsujii, H.; Ishida, T.; Kasai, K.; Okayama, Y.; Kojima, K.; Adachi, K.; Aoki, N.; Kanemura, T.; Hagishima, D.; Fujiwara, M.; Inaba, S.; Ishimaru, K.; Nagashima, N.; Ishiuchi, H.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
13-15 Dec. 2004
Page(s): 169- 172
Digital Object Identifier 10.1109/IEDM.2004.1419098
Summary: This paper discusses the root causes of the fact that only slight performance improvement of MOSFET with strained-Si substrate has been achieved in short channel region (L < 100 nm). The performance improvement in short channel region is found to de.....
AbstractPlus | Full Text: PDF IEEE CNF
4. Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs
Goto, K.; Satoh, S.; Ohta, H.; Fukuta, S.; Yamamoto, T.; Mori, T.; Tagawa, Y.; Sakuma, T.; Saiki, T.; Shimamune, Y.; Katakami, A.; Hatada, A.; Morioka, H.; Hayami, Y.; Inagaki, S.; Kawamura, K.; Kim, Y.; Kokura, H.; Tamura, N.; Horiguchi, N.; Kojima, M.; Sugii, T.; Hashimoto, K.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
13-15 Dec. 2004
Page(s): 209- 212
Digital Object Identifier 10.1109/IEDM.2004.1419111
Summary: Strain enhancing laminated SiN (SELS) is reported for the first time. Although the same thickness and stress SiN film is used, channel strain is enhanced by multi layer deposition. This effect was investigated by our simulations and experiments. To .....
AbstractPlus | Full Text: PDF IEEE CNF
5. Mobility improvement for 45nm node by combination of optimized stress and channel orientation design
Komoda, T.; Oishi, A.; Sanuki, T.; Kasai, K.; Yoshimura, H.; Ohno, K.; Iwai, A.; Saito, M.; Matsuoka, F.; Nagashima, N.; Noguchi, T.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
13-15 Dec. 2004
Page(s): 217- 220
Digital Object Identifier 10.1109/IEDM.2004.1419113
Summary: Performance improvement of CMOSFET by adopting <100>-channel direction with high tensile stress gate capping layer (GC liner-SiN) was demonstrated. For pMOSFET, higher hole mobility of <100>-channel and lesser short channel effect (SCE) results in 2.....
AbstractPlus | Full Text: PDF IEEE CNF
6. Aggressively scaled (0.143 /spl mu/m/sup 2/) 6T-SRAM cell for the 32 nm node and beyond
Fried, D.M.; Hergenrother, J.M.; Topol, A.W.; Chang, L.; Sekaric, L.; Sleight, J.W.; McNab, S.J.; Newbury, J.; Steen, S.E.; Gibson, G.; Zhang, Y.; Fuller, N.C.M.; Bucchignano, J.; Lavoie, C.; Cabral Jr, C.; Canaperi, D.; Dokumaci, O.; Frank, D.J.; Duch, E.A.; Babich, I.; Wong, K.; Ott, J.A.; Adams, C.D.; Dalton, T.J.; Nunes, R.; Medeiros, D.R.; Viswanathan, R.; Ketchen, M.; Ieong, M.; Haensch, W.; Guarini, K.W.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
13-15 Dec. 2004
Page(s): 261- 264
Digital Object Identifier 10.1109/IEDM.2004.1419127
Summary: A 0.143 /spl mu/m/sup 2/ 6T-SRAM cell has been fabricated using a planar SOI technology with mixed electron-beam and optical lithography. This is the smallest functional 6T-SRAM cell ever reported - consistent with cell areas beyond the 32 nm techno.....
AbstractPlus | Full Text: PDF IEEE CNF
7. A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography
Nackaerts, A.; Ercken, M.; Demuynck, S.; Lauwers, A.; Baerts, C.; Bender, H.; Boulaert, W.; Collaert, N.; Degroote, B.; Delvaux, C.; de Marneffe, J.F.; Dixit, A.; De Meyer, K.; Hendrickx, E.; Heylen, N.; Jaenen, P.; Laidler, D.; Locorotondo, S.; Maenhoudt, M.; Moelants, M.; Pollentier, I.; Ronse, K.; Rooyackers, R.; Van Aelst, J.; Vandenberghe, G.; Vandervorst, W.; Vandeweyer, T.; Vanhaelemeersch, S.; Van Hove, M.; Van Olmen, J.; Verhaegen, S.; Versluijs, J.; Vrancken, C.; Wiaux, V.; Jurczak, M.; Biesemans, S.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
13-15 Dec. 2004
Page(s): 269- 272
Digital Object Identifier 10.1109/IEDM.2004.1419129
Summary: This paper describes the fabrication process of a fully working 6T-SRAM cell of 0.314/spl mu/m/sup 2/ build with tall triple gate (TTG) devices. A high static noise margin of 172 mV is obtained at 0.6 V operation. Transistors with 40nm physical gate.....
AbstractPlus | Full Text: PDF IEEE CNF
8. Integration of ALD TaN barriers in porous low-k interconnect for the 45 nm node and beyond; solution to relax electron scattering effect
Besling, W.F.A.; Arnal, V.; Guillaumond, J.R.; Guedj, C.; Broekaart, M.; Chapelon, L.L.; Farcy, A.; Arnaud, L.; Torres, J.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
13-15 Dec. 2004
Page(s): 325- 328
Digital Object Identifier 10.1109/IEDM.2004.1419146
Summary: The down scaling of interconnect wiring is facing serious hurdles below 100 nm feature size due to a non-linear resistivity increase with decreasing line width. In order to investigate the increase of copper resistivity for the future technology nod.....
AbstractPlus | Full Text: PDF IEEE CNF
9. Direct plating of Cu on ALD TaN for 45nm node Cu BEOL metallization
Shih, C.H.; Su, H.W.; Lin, C.J.; Ko, T.; Chen, C.H.; Huang, J.J.; Chou, S.W.; Peng, C.H.; Hsieh, C.H.; Tsai, M.H.; Shue, W.; Yu, C.H.; Liang, M.S.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
13-15 Dec. 2004
Page(s): 337- 340
Digital Object Identifier 10.1109/IEDM.2004.1419149
Summary: Direct electro-deposition of a highly conformal and adherent Cu seed on ALD TaN by means of electro-grafting technique is presented. Both the adhesion of Cu seed to the underlying ALD TaN and EM lifetime performance were greatly enhanced by electro-.....
AbstractPlus | Full Text: PDF IEEE CNF
10. A conventional 45nm CMOS node low-cost platform for general purpose and low power applications
Boeuf, F.; Arnaud, F.; Basso, M.T.; Sotta, D.; Wacquant, F.; Rosa, J.; Bicais-Lepinay, N.; Bernard, H.; Bustos, J.; Manakli, S.; Gaillardin, M.; Grant, J.; Skotnicki, T.; Tavel, B.; Duriez, B.; Bidaud, M.; Gouraud, P.; Chaton, C.; Morin, P.; Todeschini, J.; Jurdit, M.; Pain, L.; De-Jonghe, V.; El-Farhane, R.; Jullian, S.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
13-15 Dec. 2004
Page(s): 425- 428
Digital Object Identifier 10.1109/IEDM.2004.1419177
Summary: In this work, a low-cost 45nm node platform for general purpose and low power applications based on conventional bulk approach is proposed. Performant Lg=30nm/45nm devices with SiON gate oxide, shallow junctions and process induced strain are demons.....
AbstractPlus | Full Text: PDF IEEE CNF
11. Enhanced ballisticity in nano-MOSFETs along the ITRS roadmap: a Monte Carlo study
Eminente, S.; Esseni, D.; Palestri, P.; Fiegna, C.; Selmi, L.; Sangiorgi, E.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
13-15 Dec. 2004
Page(s): 609- 612
Digital Object Identifier 10.1109/IEDM.2004.1419235
Summary: In this work we have simulated the I/sub ON/ and its ballistic limit I/sub BL/ of MOSFETs designed according to the 2003 roadmap down to the 45 nm node, by using a full-band, self-consistent Monte Carlo simulator with quantum mechanical corrections......
AbstractPlus | Full Text: PDF IEEE CNF
12. Performance comparison between carbon nanotube and copper interconnects for GSI
Naeemi, A.; Sarvari, R.; Meindl, J.D.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
13-15 Dec. 2004
Page(s): 699- 702
Digital Object Identifier 10.1109/IEDM.2004.1419265
Summary: The performances of minimum-size copper and carbon nanotube interconnects are compared for various ITRS generations. Results offer important guidance regarding the nature of carbon nanotube technology development needed for improving interconnect pe.....
AbstractPlus | Full Text: PDF IEEE CNF
13. Al/sub 0.3/Ga/sub 0.7/N/Al/sub 0.05/Ga/sub 0.95/N/GaN composite-channel HEMTs with enhanced linearity
Jie Liu; Yugang Zhou; Rongming Chu; Yong Cai; Chen, K.J.; Kei May Lau
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
13-15 Dec. 2004
Page(s): 811- 814
Digital Object Identifier 10.1109/IEDM.2004.1419299
Summary: We report an Al/sub 0.3/Ga/sub 0.7/N/Al/sub 0.05/Ga/sub 0.95/N/GaN composite-channel HEMT with enhanced linearity. Through channel engineering, i.e. inserting a 6-nm thick AlGaN layer with 5% Al composition in the channel region, a composite-channel.....
AbstractPlus | Full Text: PDF IEEE CNF
14. 45 nm nMOSFET with metal gate on thin SiON driving 1150 /spl mu/A//spl mu/m and off-state of 10nA//spl mu/m
Henson, K.; Lander, R.J.P.; Demand, M.; Dachs, C.J.J.; Kaczer, B.; Deweerd, W.; Schram, T.; Tokei, Z.; Hooker, J.C.; Cubaynes, F.N.; Beckx, S.; Boullart, W.; Coenegrachts, B.; Vertommen, J.; Richard, O.; Bender, H.; Vandervorst, W.; Kaiser, M.; Everaert, J.-L.; Jurczak, M.; Biesemans, S.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
13-15 Dec. 2004
Page(s): 851- 854
Digital Object Identifier 10.1109/IEDM.2004.1419312
Summary: We demonstrate for the first time that nMOS devices with PVD TaN gate on 1.2 nm EOT SiON can be fabricated with high drive currents. On state currents of 1150 /spl mu/A//spl mu/m (I/sub off/ < 10 nA//spl mu/m) at 1.2 V and 810 /spl mu/A//spl mu/m (I.....
AbstractPlus | Full Text: PDF IEEE CNF
15. Enhanced dielectric-constant reliability of low-k porous organosilicate glass (k = 2.3) for 45-nm-generation Cu interconnects
Ryuzaki, D.; Sakurai, H.; Abe, K.; Takeda, K.; Fukuda, H.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
13-15 Dec. 2004
Page(s): 949- 952
Digital Object Identifier 10.1109/IEDM.2004.1419341
Summary: The mechanism of the dielectric-constant increase in porous organosilicate glasses (OSGs) under electric-field stress has been revealed for the first time, where the dielectric-constant increase is caused by the oxidation of methyl groups in porous .....
AbstractPlus | Full Text: PDF IEEE CNF
16. Thermally robust Cu interconnects with Cu-Ag alloy for sub 45nm node
Isobayashi, A.; Enomoto, Y.; Yamada, H.; Takahashi, S.; Kadomura, S.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
13-15 Dec. 2004
Page(s): 953- 956
Digital Object Identifier 10.1109/IEDM.2004.1419342
Summary: Cu interconnects reliability has been drastically improved by the introduction of Ag doped Cu (Cu-Ag) alloy seed. The usage of Cu-Ag remarkably suppressed stress induced voiding (SiV) in the lower wide metal which appeared by the additional anneal t.....
AbstractPlus | Full Text: PDF IEEE CNF
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