From the ADVANCE PROGRAM of the 2007 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE FEBRUARY 11,12,13,14,15
IEEE SOLID-STATE CIRCUITS SOCIETY/IEEE SAN FRANCISCO SECTION, BAY AREA COUNCIL/UNIV. OF PA.
SESSION 5
MICROPROCESSORS
Chair: Stefan Rusu, Intel, Santa Clara, CA
Associate Chair: Jim Warnock, IBM T.J. Watson, Yorktown Heights, NY
5.1 --------------- 1:30 PM ------------------
Design of the POWER6™ Microprocessor
J. Friedrich1, B. McCredie1, N. James1, B. Huott2, B. Curran2, E. Fluhr1, G. Mittal1, E. Chan1, Y. Chan2, D. Plass2, S. Chu1, H. Le1, L. Clark1, J. Ripley1, S. Taylor1, J. Dilullo1, M. Lanzerotti3
1 IBM, Austin, TX
2 IBM, Poughkeepsie, NY
3 IBM T.J. Watson, Yorktown Heights, NY
The POWER6™ microprocessor combines ultra-high frequency operation, aggressive power reduction, a highly scalable memory subsystem, and mainframe-like reliability, availability, and serviceability. The 341mm2 700M transistor dual-core microprocessor is fabricated in a 65nm SOI process with 10 levels of low-k copper interconnect. It operates at clock frequencies over 5GHz in high-performance applications, and consumes under 100W in power-sensitive applications.
5.2 -------------- 2:00 PM ----------------
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS
S. Vangal1, J. Howard1, G. Ruhl1, S. Dighe1, H. Wilson1, J. Tschanz1, D. Finan1, P. Iyer2, A. Singh2, T. Jacob2, S. Jain2, S. Venkataraman2, Y. Hoskote1, N. Borkar1
1 Intel, Hillsboro, OR
2 Intel, Bangalore, India
A 275mm2 network-on-chip architecture contains 80 tiles arranged as a 10×8 2D array of floating-point cores and packet-switched routers, operating at 4GHz. The 15-FO4 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. The 65nm 100M transistor die is designed to achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W.
5.3 ------------ 2:30 PM ------------------
A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption
Y. Yoshida1, T. Kamei1, K. Hayase1, S. Shibahara1, O. Nishii1, T. Hattori1, A. Hasegawa1, M. Takada2, N. Irie2, K. Uchiyama2, T. Odaka2, K. Takada3, K. Kimura4, H. Kasahara4
1 Renesas Technology, Tokyo, Japan
2 Hitachi, Tokyo, Japan
3 Hitachi ULSI, Tokyo, Japan
4 Waseda University, Tokyo, Japan
A 4320MIPS four-core SoC that supports both SMP and AMP for embedded applications is designed in 90nm CMOS. Each processor-core can be operated with a different frequency dynamically including clock stop, while keeping data cache coherency, to maintain maximum processing performance and to reduce average operating power. The 97.6mm2 die achieves a floating-point performance of 16.8GFLOPS.
5.4 ------------ 3:15 PM -----------------
An Integrated Quad-Core OpteronTM Processor
J. Dorsey1, S. Searles1, M. Ciraula1, E. Fang2, S. Johnson1, N. Bujanos1, R. Kumar2, D. Wu1, M. Braganza1, S. Meyers1
1 AMD, Austin, TX
2 AMD, Sunnyvale, CA
An integrated quad-core x86 processor is implemented in a 65nm 11M SOI CMOS process. Based on an enhanced OpteronTM core, the SoC-developed processor employs power- and thermal-management techniques throughout the design. The SRAM cache designs target process variation considerations and future process scalability. A DDR2/DDR3 combo-PHY and HT3 I/Os provide high-bandwidth interfaces.
5.5 ------------- 3:45 PM -------------------
A 25W SoC with Dual 2GHz PowerTM Cores and Integrated Memory and I/O Subsystems
Z. Chen, P. Ananthanarayanan, S. Biswas, H. Chen, C. Chng, S. Desai, S. Desai, D. Go, V. von Kaenel, M. Kanchana, J. Kassoff, F. Klass, W. Ku, T. Li, X. Lu, J. Lin, K. Malik, R. Notani, E. Shiu, C. Shuler, S. Santhanam, G. Scott, T. Takayanagi, P. Trivedi, J. Wang, G. Yiu
PA Semi, Santa Clara, CA
An SoC is presented with dual 2GHz PowerTM cores, coherent crossbar interconnect, 2MB L2 cache, and memory and I/O subsystem. The chip consumes a maximum of 25W of power. The 115mm2 die is implemented in a 65nm 8M process with low-power design techniques. Circuits to improve system performance under power constraints are discussed.
5.6 -------------- 4:15 PM ------------------
Implementation of the 65nm Dual-Core 64b Merom Processor
N. Sakran, M. Yuffe, M. Mehalel, J. Doweck, E. Knoll, A. Kovacs
Intel, Haifa, Israel
Merom is a dual-core 64b processor implementing the CoreTM architecture. The 143mm2 die has 291M transistors in a 65nm 8M process. The shared 4MB 16-way L2 cache uses PMOS power gating to minimize leakage. The processor operates in a wide core frequency range of 1 to 3GHz, a bus frequency range of 666 to 1333MHz and voltage range of 0.85 to 1.325V, while providing 40% better power performance.
5.7 --------------- 4:45 PM ------------------
An 8-Core 64-Thread 64b Power-Efficient SPARC SoC
U. Nawathe, M. Hassan, K. Yen, L. Warriner, B. Upputuri, D. Greenhill, A. Kumar, H. Park
Sun Microsystems, Sunnyvale, CA
The 8-core 64-thread 64b power-efficient 2nd-generation Niagara SPARC SoC has 4MB L2 cache with one x8 PCI-Express, two 10G Ethernet (XAUI), and 8 FBDIMM ports. The on-chip SerDes provide greater than 1Tb/s bandwidth. The 500M transistor chip with a die size of 342mm2 is implemented in a 11M 65nm triple-Vt CMOS process.
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Conclusion 5:15 |
