"design for manufacturability (DFM)"
"Most chip designers today are as concerned about power as they are about timing, if not more so. On sub-100nm processes, leakage power is becoming the dominant component of overall power consumption and at 65nm, leakage can account for more than 50% of the total."
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Electrical DFM – Focusing on What Matters to Chip Designers
Do chip designers really care about design for manufacturability (DFM) and yield? Dave Reed of Blaze DFM thinks that if they don't, they need to!
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By Dave Reed
Do chip designers really care about design for manufacturability (DFM) and yield? When it comes to functional failures caused by random defects, probably not. There isn't much that chip designers can do to reduce the number of random defects that typically manifest themselves as shorts and opens. There are some things that they can do during physical layout, but these usually amount to "band aid" fixes that improve yield a few percentage points, at best.
What about parametric failures – chips that fail to meet power and timing specifications? At 130nm and above, parametric failures are negligible compared to functional failures. At 90nm, they become significant, and at 65nm, parametric failures become the single most critical yield-limiting factor.
Given that chip designers spend a lot of their design time doing everything they can to ensure that their chips meet power and timing specs, they care a lot about these types of failures. But, what can chip designers do to influence the manufacturing process so as to maximize parametric yield?
"Cross your fingers and hope for the best." Sounds rather comical, but in reality, this is a very common approach. Once the design is verified by the golden signoff tool and handed off to manufacturing, it's out of the designers' hands and they have to rely on manufacturing to ensure adequate parametric yield of their design.
Can DFM techniques increase parametric yield?
Today, many of the approaches that are commonly referred to as DFM techniques only address catastrophic defects. These techniques include spreading wires, doubling vias, and identifying critical areas in the chip that are especially susceptible to defects.
While these techniques may be useful in reducing functional failures and increasing overall yield by a few percentage points, they do nothing to make chips faster or less power hungry – and they completely ignore the more important category of parametric failures.
However, there is a newly emerging generation of Electrical DFM solutions specifically created to maximize parametric yield for chips implemented with sub 100nm process technologies.
Electrical DFM solutions work to foster communication between design and manufacturing. They drive design requirements into manufacturing and move manufacturing awareness upstream into design. In order to be widely adoptable, electrical DFM solutions must be minimally disruptive to existing design flows and the handoff to manufacturing.
Electrical DFM solutions take advantage of the fact that there is a lot of information about the manufacturing process that simply isn't being put to good use during design and, conversely, that there is a lot of useful information about the design that isn't being used during manufacturing. This manufacturing information is readily available as part of a design kit; it's not the detailed top-secret information that foundries are often reluctant to reveal to the outside world.
How can chip designers make use of manufacturing information to improve parametric yield?
Here is one example. Most chip designers today are as concerned about power as they are about timing, if not more so. On sub-100nm processes, leakage power is becoming the dominant component of overall power consumption and at 65nm, leakage can account for more than 50% of the total.
Electrical DFM tools can optimize transistor gate length on a gate-by-gate basis to reduce leakage and improve timing. What this amounts to is tweaking the power and performance characteristics of every transistor in the design.
How can chip designers possibly influence the details of transistor gate length during fabrication? Don't the physical design tools use fixed standard cells?
In fact, no changes to standard cell layout are required! The first step in any advanced process is optical proximity correction (OPC) software. By converting design requirements into specific OPC directives, electrical DFM tools can configure the manufacturing process to implement, in silicon, the transistor-level optimization that was performed by the electrical DFM solution.
Sounds like a lot of work. Is it worth it?
If architected and implemented correctly, electrical DFM solutions do not require any major disruptive changes to the design flow, the golden signoff, the handoff to manufacturing, or to the manufacturing process. Well-conceived electrical DFM solutions are remarkably transparent to all of the affected parties.
Electrical DFM solutions perform extremely complex optimizations on literally tens of millions of transistors. However, they do not lengthen the time needed to tape out a chip because the optimizations are performed in parallel with design steps that are already part of the standard design flow.
In terms of financial impact, electrical DFM solutions have been proven in silicon to increase parametric yield by double-digit percentage points. This can have a profound impact, not only on the profitability of the design, but on the amount of time that it takes to bring a product to market as well.
Summary
Electrical DFM solutions use process information to optimize the design for power and timing. They then convert the results of that optimization into manufacturing directives that tailor the manufacturing process for the specific requirements of each design. Electrical DFM solutions offer dramatic results in terms of reduced leakage power, increased parametric yield, and business impact, all at a very low cost of adoption and ownership. Through their unique awareness of both design and manufacturing, electrical DFM solutions enable chip designers to fully realize the power of today's most advanced process technologies.
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Dave Reed, co-founder and vice president of marketing and business development at Blaze DFM. Mr. Reed has over 20 years of experience building startups into successful enterprises with companies such as Cadence, Cooper & Chyan Technology, and Tangent Systems. He started his career as an IC design engineer with Commodore Business Machines. He has a B.S.E.E. from Lehigh University.
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