Advanced Micro Devices - Moderated (AMD) Message Board

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Technology Stocks : Advanced Micro Devices - Moderated (AMD)

AMD 220.28

-0.6%

11:40 AM EST

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To: Ali Chen who wrote (225603)	2/8/2007 6:37:20 PM
From: pgerassi	Read Replies (1) of 275872

Dear Ali: HT traffic for I/O, at most, uses some XBAR resources. But the XBAR is somewhere between 8 and 32 bytes wide DDR running at CPU clock. So for a 2GHz K8, thats somewhere between 32 to 128GB/s. A few GB/s I/O traffic isn't going to cause it to block memory traffic. With HT 1.0, each HT link only has up to 6.4GB/s of traffic maximum. With DDR2-800, you get 12.8GB/s of memory plus 19.2GB/s for three links for a total of 32GB/s. That's the minimum XBAR throughput. So fully loaded, HT traffic can't reduce memory BW or increase its latency whether its locally or remotely demanded. With Barcelona, HT 3.0 and DDR3-1200, there is 4 HT links at 20.8GB/s each plus 19.2GB/s for DDR3-1200 for a total of 102.4GB/s. Look for XBAR to be made 32 bytes wide (256 bits) to accommodate all the HT and memory traffic even at 2GHz. It dovetails nicely with 256 bit wide L1 to L2 to L3 widths. Given that XBAR will be 128GB/s, memory BW can be up to DDR3-2800 (44.8GB/s). That is a lot of leeway for future memory speeds. Pete

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