SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 213.49-0.1%Feb 11 3:59 PM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Ali Chen who wrote (225597)2/10/2007 10:02:39 AM
From: Dan3Read Replies (1) of 275872
 
Re: Unfortunately, I don't see much in it that would address optimisation of outside memory traffic, the area where AMD is currently quite behind Intel.

There is a giant weakness in AMD's design right now, and that's the core's connection to cache. That's (FINALLY!) being fixed through a 100% increase in bandwidth. The x86 architecture compensates for its lack of registers (relative to MIPS, IA64, etc.) through heavy use of L1. That core to cache choke point is so overwhelming that the connection to outside memory traffic is rarely relevant - chopping that connection's speed in half has about a 3% to 5% affect on overall performance (populating only one memory channel).
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext