"i don't know about you but my smallest fpga design takes nearly 4 hours in ise. i certainly can't afford to wait for it to finish to look-at my next client's item with ncverilog or matlab. in the mean time, the background indexer is working on the new pdfs i downloaded, outlook is fetching & filtering mail, ... you get the idea."
Then there is certainly something wrong with the way you are doing things. First, if it takes that much time, get a bigger FPGA, or get a faster computer, or use the incremental design methodology, it is available now in ISE. Second, since I too cannot afford to SLOW DOWN my compiles by messing with disk access patterns, cache pollution, and risking that some Windows "security patch" would block something or hang something, I have two more machines under my desk where I do other job like mail, pdf, software download, burning CD/DVDs, or looking at gerbers or making them. And I don't do auido player at work. Do you get the idea now?
Also, if you does not know about caveats of timing between behavioral and post-place-and-route simulations, you never had a challenging design that worked in reality.
Speaking about "multi-core, multi-threaded environments", I already tried to explain to you that there is substantial difference between multi-threaded but integrated application, different applications with different demands for resources, and running several identical copies of the same application as SPECrate does. So the misconception is still there, and is clearly on your side.
- Ali |
