Advanced Micro Devices - Moderated (AMD) Message Board

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Technology Stocks : Advanced Micro Devices - Moderated (AMD)

AMD 192.49

-4.0%

Feb 5 3:59 PM EST

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To: combjelly who wrote (228393)	3/20/2007 3:59:07 AM
From: DDB_WO	Read Replies (1) of 275872

A K10 MCM would cause new problems, even not related to probably missing MCM experience, but to simple stuff like the necessity to feed all needed different voltages (via enough power pins) to the multiple power planes present on the MCM. This is already a limitation causing all 4 cores to run at the same voltage, which just could be lowered depending on the highest P-state being active on the 4 cores. From the I/O POV the inter-chip communication would be ok (there are 4 HT links on each die and finally only 3 have to go out of the current S1207 package, leaving 3 HT links unused) but the cache coherency traffic (now caused by 8 cores instead of 4) and mem bandwidth will become even more of a bottleneck. I think, it is even more likely, that we see SMT and/or trace caches from AMD before they produce MCMs to get an 8 core CPU. (MCMs for ideas seen in the Torrenza initiative I have excluded here) One statement from some AMD guy (Rivas?) mentioning MCMs was probably more related to time to market issues than to design for manufacturing, performance or power consumption advantages.

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