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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 203.14-0.8%Jan 9 9:30 AM EST
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To: Sarmad Y. Hermiz who wrote (228516)3/20/2007 3:09:02 PM
From: pgerassiRead Replies (3) of 275872
 
Dear Sarmad:

This claim:

A more troubling issue is that SOI has higher “thermal resistance” than bulk CMOS. As a result, SOI transistors are forced to run at temperatures higher than necessary. Higher operating temperatures could cause long-term reliability problems.

Has been debunked by simple emperical evidence. See:

jobinyvon.com
soitec.com

You see that the layer is less than 100nm (1000A) thick. The wafer is 775um (microns) thick. That means the bulk silicon is 7700 times thicker than the oxide layer. The thermal resistance added is at most 0.1%. It is another Intel claim which is vastly over exaggerated. Intel's IHS adds far more thermal resistance than a bare die (shown to be over 10%), yet where is their claim that the IHS forces them to use far lower frequencies. They likely have far more variation due to the mating imperfections at the IHS die boundry.

And if they are so far off that claim, the initial one is likely to be equally far off. Heck one quarter of APM likely increases switching speeds more than the difference in published speeds. Beside what does Intel consider comparable leakage currents? And what leakage currents are they comparing? Do they include substrate leakage? If they don't, the statement is irrelevant and thus, worthless,

Pete
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