Doug, Re: MY-- It's on the order of my post of last ?December? indicating my Opinion that Intel had gotten, finally, their 65 Nm CMW production working properly. -- to which you were responding.
Well that's silly. CMW overclocked like mad out of the gate
Ok, after a long weekend of skiing I'me up to near real time.
IMO you are once again, as lots of folks have in the past, confusing bin splits for yield.
This part is pure speculation on my part.
IMO INTC expected better results from 45 Nm, as did AMD, and designed the CMWs aggressively for speed. INTC got the high bins but not many parts. (Poor yield of functional parts. IMO high bins are most important for PR than anything else, indeed, low watts. High bins in low volumes have a panache )
Last ?December? I posted that, IMO, INTC had most of their yield problems fixed. That was nearly a year after INTC announced start of 65 Nm manufacture, IIRC.
Though I'm much less sure now of the current AMD status my *Feel* is that their 65 Nm is, now about where they hoped it'd be about 9 months ago, about 12 months behind INTC.
Re: and it was Intel's fastest ramp ever. Production was working from the get go, earlier than expected.
Fastest in terms of units not fastest in terms of percentage of production IIRC. Look at the P-III vs PIV ramp as opposed to the PIV-CMW ramp.
But, then, PIV had known problems at launch.
It's the unknown problems that're scary,
-tgp |
