"It seems as though Intel has placed their bet on EUV making it in time for 22nm, while AMD has taken the other side of it."
Good summary of the situation. However, I don't think you got the conclusion right.
As smooth often does, he doesn't recognize, I'll let others draw their conclusions as to why, that AMD and Intel have different constraints. And Intel makes the best choices for them, and IBM/AMD optimizes for their situation.
Intel had to go with very precise positioning of the mask layers at 90nm. My guess is they were trying to compensate for the power consumption of the P4, but other possibilities exist. So they already had that technology in place, and have built and are building extra fabs to compensate for the lower wafer velocity. With those two things already in hand, double patterning is an obvious choice.
AMD, however, is usually capacity constrained. One aspect of APM is to increase wafer velocity by better scheduling. As an AMD spokesman mentioned, they are trying to reduce transit time from 3T to 2T, where T is the ideal minimum time to process a wafer. And they have had some success, just look at how they managed to increase the number of wafers per month at Fab30. So, for AMD, it made more sense to pay a little more to go with immersion instead of developing more precise mask positioning and taking a capacity hit with double patterning.
Which probably explains the New York fab. They probably could have ping-ponged back and forth between the two in Dresden, with possibly some expansion with the extra land they have there, but that won't work if they have to face double patterning in a couple of generations.
I don't think Intel is gambling on EUV. At this point, they would be foolish to. They just took the most cost effective path for their situation. |
