Last year's VLSI Symp included these designs from Samsung and Toshiba:
15.4 - 4:40 p.m.
World Smallest 0.34µm2 COB Cell 1T1C 64Mb FRAM with New Sensing Architecture and Highly Reliable MOCVD PZT Integration Technology, Y.M. Kang, H.J. Joo, J.H. Park, S.K. Kang, J.-H. Kim, S.G. Oh, H.S. Kim, J.Y. Kang, J.Y. Jung, D.Y. Choi, E.S. Lee, S. Y. Lee, H.S. Jeong, K. Kim, Samsung Electronics Co. Ltd., Kyungki-Do, Korea
We have demonstrated a 0.34um2 COB cell 1T1C 64Mb FRAM at 150nm technology node. The signal window between of 64M bit cells was 300mV at 85°C, 1.6V VDD. This wide signal window was achieved by advanced anneal technology and optimized capacitor layout, from which the variation of individual cell charge was greatly improved, with 70nm thick MOCVD PZT. The multi-reference cell equalizing scheme, greatly improved the variation of the reference cell signal. As a result, no single bit failure was found in our 1T1C 64Mb FRAM after 500hour bake at 150°C.
15.5 - 5:05 p.m.
High Density and High Reliability Chain FeRAM with Damage-Robust MOCVD-PZT Capacitor with SrRuO3/IrO2 Top Electrode for 64Mb and Beyond, O. Hidaka, T. Ozaki, H. Kanaya, Y. Kumura, Y. Shimojo, S. Shuto, Y. Yamada, K. Yahashi, K. Yamakawa, S. Yamazaki, D. Takashima, T. Miyakawa, S. Shiratake, S. Ohtsuki*, I. Kunishima, A. Nitayama, Toshiba Corporation, Yokohama, Japan, *Toshiba Microelectronics Corporation, Yokohama, Japan
An excellent 64Mb chainFeRAMTM using a highly reliable capacitor with damage-robust MOCVD-PZT and SrRuO3/IrO2 top electrode (TE) is successfully demonstrated for the first time. A very large signal margin of 540mV at 1.8V is achieved for the capacitor as small as 0.19µm2. Large sensing margin is well maintained after 85°C storage, and 10 years lifetime is successfully guaranteed. The combination of damage-robust MOCVD-PZT and optimized SrRuO3/IrO2 TE as well as a sophisticated ‘chain’ structure that has a small bit line capacitance (Cb) nature shows excellent reliability and scalability. This work demonstrates that high density 256Mb chain FeRAM with 0.1µm2 planar capacitor can be realized.
This year Samsung has a working 64Mb embedded design down to nearly 1/3rd the cell size of TI's 4Mb chip:
Session 12B-3
130 nm-Technology, 0.25 µm2, 1T1C FRAM Cell for
SoC (System-on-a-Chip)-Friendly Applications
Y.K. Hong, D.J. Jung, S.K. Kang, H.S. Kim, J.Y. Jung, H.K. Koh, J.H. Park, D.Y. Choi, S.E. Kim, W.S. Ann, Y.M. Kang, H.H. Kim, J.-H. Kim, W.U. Jung, E.S. Lee, S.Y. Lee, H.S. Jeong and K. Kim, Samsung Electronics Co. Ltd., Korea
We have successfully demonstrated a world smallest 0.25 um2 cell 1T1C 64 Mb FRAM at a 130 nm technology node. This small cell size was achieved by scaling down a capacitor stack, using the following technologies: a robust glue layer onto the bottom electrode of a cell capacitor; 2-D MOCVD PZT technology, novel capacitor-etching technology; and a top-electrode-contact-free (TEC-free) scheme. The new FRAM cell is suitable for a mobile SoC (System-on-a-Chip) application. This is due to realization of four metal technology required for high-speed logic devices. As a result, the remanent polarization value of 32 uC/cm2 was achieved after full integration and the sensing window was evaluated to 370 mV at 85 C, 1.3 V.
I am hoping we see Toshiba's process design hit the market within a year at 64Mb, but it looks like Samsung's method may be better than TI's for true "Front End" embedded apps. It's just amazing what the added research money and effort can do.
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