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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 246.76-0.5%Nov 14 9:30 AM EST
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To: eetnoyer who wrote (230076)4/16/2007 1:33:29 PM
From: pgerassiRead Replies (1) of 275872
 
Dear Eetnoyer:

Double Patterning doesn't get you to 32nm with 65nm tools. You have to go to Quad Patterning at 14 times the steps as immersion requires per 32nm mask. With this you get about 30% of the wafer throughput at much lower yields. A rough estimate that at a given clean room floorspace, it takes between 4 and 5 fabs to do quad patterning as 32nm immersion. And I am not even taking the layout hit due to restrictions on allowable mask patterns (some 32nm masks can not be done with 65nm quad patterning). This will cause quad patterned 32nm dies to be bigger (or less dense) than 32nm immersion dies.

Double exposure 45nm dies are bigger than immersion 45nm dies, but not as bad as it will be at 32nm. You see this by the cache size only goes up by 1.5 times for Intel from Conroe to Penryn (4MB -> 6MB) while Barcelona to Shanghai goes up by 2 using all cache L2 and L3 (4x0.5MB+2MB = 4MB -> 4x0.5MB+6MB = 8MB). So by doing this again to get to the 32nm hit, a 32nm Penryn will have 9MB of shared L2 versus a 32nm Shanghai having 4x0.5MB+14MB =16MB. While at 45nm Intel loses its cache advantage, at 32nm Intel falls behind AMD. Boosting the Intel die size to compensate, will require twice the fabs over the hit in throughout and yields. You can see why Intel has to go to ODMC and CSI at 45nm or get really screwed come 32nm.

ZRAM would exacerbate this effect. With ZRAM, Shanghai would be at 4*0.5MB+30MB = 32MB. 32nm Shanghai with ZRAM would be at 4*0.5MB+70MB = 72MB. A Fusion CPU based on the latter would be like tying a 4GHz DC K10 to a R600 GPU in a 35W TDP laptop. That would give Intel nightmares.

Pete
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