SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 259.65+2.3%3:59 PM EST
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: dougSF30 who wrote (231507)4/25/2007 4:37:16 PM
From: Joe NYCRead Replies (2) of 275872
 
Doug,

Petz, so your "belief" is that cores can be disabled, but L3 cannot.

I think the point Petz is trying to make is that since L3 is goind to be highly redundant, the likelihood of defect in L3 is small. Therefore, there has to be a non-L3 die.

Actually, since DCs with L3 are likely to be much smaller volume than non-L3, it is possible that DCs with L3 will come (at least initially), from partially defective QC chips.

That way, there would be only 2 types of dies at the beginning of production, QC with L3 and DC without L3.

Joe
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  

HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2026 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News