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AMD 203.14-0.8%Jan 9 9:30 AM EST
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To: Ali Chen who wrote (943)10/3/1997 10:12:00 PM
From: Yousef   of 6843
 
Ali,

Re: "The speed of a device is limited not only by the gate switch delays, but mainly due to
gate complexity of CPU units in pipelines ..."

This is just plain foolishness on your part, Ali. Please see my previous
post comparing the architectures:

siliconinvestor.com

Notice that the PII and PPro complete 3 instructions per cycle versus
2 per cycle for the K6. Also, the PII and P5MMX have pipelined MMX
capability that the K6 lacks and please note that the K6 also lacks
a pipelined FPU. So, your theory is full of holes (once again !!)
The K6 has so many more FET's because it has a much larger L1 cache, not
due to pipelining or CPI (cycles per instruction)!!

Also as I have posted before, an IC process can be simply measured
by the following formulas:

Power ~ CV^2F , C= Capacitance, V= Supply Voltage, F= Frequency

Performance ~ I/(CV) , I= Idsat Drive Current

So as we move from one IC generation to the next, the strategy is to
maintain the same capacitance and Idsat (FET drive current) while
lowering the operating voltage. The development team that can maintain
high drive currents at the lowest voltage WINS !! It is very
simple, Ali. This is why the PII runs at 300mhz (.35um process) and
the K6 runs at 233mhz (.35um process).

Hopefully this will help straighten you out.

Make It So,
Yousef
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