Dear Wbmw:
You assume a lot in your estimates. Always to AMD's detriment. AMD includes the memory controller, Intel does not. You assume that AMD uses the maximum which is tested at all Tcase temperatures within the operating range. Intel assumes 35C for the lower 8W per note 4. The E4300 uses 50C Tcase which would leak more than it would at 35C. And the 8W also assumes typical usage of a typical part. No AMD A64 X2 4800+ (2.5GHz) or 5000+ (2.6Ghz) uses more than the specified 3.79W in C1E (5000+) or 3.95W in C1E (4800+). That is less than half of your 8/12/22W TDP with memory control included. The 12.25W from FX74s include 3 running HT links with one being a coherent with ECC and scrubbing of DDR2 memories with all caches. The X6800 and X6850 do not do any scrubbing of ECC memory in their C1E mode including their caches according to their datasheet.
BTW, why doesn't Intel specify the voltages and currents used in states C1 and C1E? At least AMD shows all P states and the associated maximum voltages and currents. And AMD can return from its C1E faster than Intel can from their C1E as AMD just has to start the HT link and come out of halt state. Intel has to wait for the VRM to increase voltage to the minimum P state, increase clock, do the same for the chipset, then resync the caches and finally come out of the halt state. Merom coming from C4 has to have the VRM increase voltage, start the clocks, initialize the caches, do the same for the chipset, reload the registers and other such, then finally come out of the halt state. Initially there are many cache misses due to all caches being empty, so it starts very slowly. 32K cache lines take a long time to refill through the slow 800MHz QDR FSB.
As to comparisons, Tyler based G1 stepping Turion X2s are coming out and they are the same 65nm process generation as are the Core 2s. Tyler is at 2.3GHz as is Merom at 2.33GHz (667MHz QDR FSB) or 2.4 GHz (800MHz QDR FSB). Tyler may go faster as this is just the initial speeds. Merom is over and done with clock increases (unless Penryn flops).
Penryn will battle Griffith which does have a C4 state where the cores are off being on separate VDD voltage planes, but the memory and I/O are on being on the third voltage plane set, VLDT/VDDIO/VDDA/VDD(NB+ODMC). Griffith will also have a lot of internal gating to turn off short term unused functional units. This will extend into the chipset, both iGPU and SB.
AMD does have a possible bomb that will blow up Intel's mobile plans all to hell, 45nm Fusion in 2008. Intel would have to stop using any benchmarks using transcoding, 3D generation or stream processing that are favorites through P4 and Core 2 CPUs. All of a sudden, Intel would lose those by a mile. And while AMD could power gate the GPU, Intel couldn't do the same as it has to use third party GPUs for the performance side, since its GPUs leave a lot to be desired in that area.
Pete |
