SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 231.83+1.7%Jan 16 9:30 AM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: BUGGI-WO who wrote (236951)7/24/2007 4:21:52 PM
From: pgerassiRead Replies (2) of 275872
 
Dear Buggi:

On a MCM, HT links could easily go to the max speed and even use 32/32 cHT links over such a short distance. The older dies had 3 16/16 HT links so one 16/16 HT link can still go to the socket S1g and the other two combine to form the 32/32 HT link to the GPU. 5.2GT/s for 32/32 HT3 is 21.6GB/s each way. 2 DDR3/1600 channels have 25.6GB/s of BW available so it would be a good match for stream processing as well. It would be more BW available than the current R630 gets (Radeon HD 2600XT). At 80 stream processors and likely 45nm clocks of 1GHz would yield 160Gflops of SP or 80Gflops of DP. TDPs of the GPU would be around 35W or so. Couple that with a 35W Griffith core and you get 70W TDPmax with all 3 cores (2 CPU and 1 GPU) going full blast. The DTR market used to have 65W and 89W TDP CPUs in them.

The next generation in 2009 then would likely put both on the same die having a NB that moves 64 byte messages at 1 per clock. So a 2GHz Fusion would move 128GB/s in the NB and use 2 DDR4/3200 channels for 51.2GB/s all for 35W TDP. It might be on AMD's 32nm SOI with ZRAM for extra large L3 caches (64-96MB) or TSMCs 32nm bulk with ordinary SRAM L3 caches (14MB).

Pete
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext