Dan, do you not understand the difference between line yields and die yields...?
The loan agreement says that AMD's line yield cannot fall below 75%. Line yield refers to the number of wafers that get completely scrapped. Out of the thousands of wafer starts every week, sometimes a few lots experience a problem, or a machine breaks down in the middle of its procedure, forcing the complete disposal of all of the wafers in the lot. Clearly, getting below 75% line yield would mean a quarter of all wafers are being scrapped, which would be a pitiful state of affairs. I'm sure AMD's line yields are in the 90s of percentile.
On the other hand, die yields are an entirely different story. These depend on the size of the die, and are usually measured in defect density, not in percentage of die (which varies from design to design). There is no way the loan agreement would refer to die yield, since there's no way even world class yields would allow a 284mm^2 die to yield at 75%.
Based on this document, the ITRS designs specifications to allow for 0.22 defects/cm2 for high volume MPUs.
itrs.net
siliconinvestor.com
For a 284mm^2 die on 300mm wafers, this would be 55% die yield. AMD's defect density, however, is somewhat less than 0.5D/cm2, which lowers yield to around 29%. This is far from world class, but may easily satisfy the stipulations in your previous link. |
