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Technology Stocks : Advanced Micro Devices - Moderated (AMD)

AMD 203.14

-0.8%

Jan 9 9:30 AM EST

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To: j3pflynn who wrote (238284)	8/7/2007 2:48:59 PM
From: Petz	Read Replies (2) of 275872

I wonder if AMD had to pay Intel to use the SSE4a instructions -- most likely in IP, though it could be cash or royalties. IIRC, it's usually about a year before AMD clones a new SSEx, so the immediate availability of a subset is somewhat unusual. A CPU-Z screenshot of a Woodcrest engineering sample from May 2006 shows that C2D was supposed to support SSE4. techreport.com So obviously a CPU-Z text string does not prove anything, just that at some point in time, C2D was supposed to support SSE4. The instructions, originally called Gesher New Instructions were divulged September 2006 at IDF. uk.theinquirer.net The original 8-page white paper states that not all of SSE4 will be implemented in Penryn (footnote at end of paper). It lists 53 instructions. ftp://download.intel.com/technology/architecture/new-instructions-paper.pdf Intel's 45nm white paper says that SSE4, as implemented in Penryn, includes nearly 50 new Intel® SSE4 instructions, but doesn't list them by opcode. intel.com It also states that Nehalem will add some SSE4 instructions so these are probably the ones missing from Penryn. They also mention some new Nehalem instructions called ATA. Of all the SSE4 instructions, the one that I believe gives the most bang for the buck is the streaming load instruction. Streaming load instruction (important for video processing, imaging, and applications that share data between the graphics processor and processor)... improves the bandwidth for reading data from a graphics frame buffer... this instruction can enable an up to 8X theoretical improvement in read bandwidth. Is this one of the ones included in AMD's SSE4a subset? Petz

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