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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 249.86+0.1%10:12 AM EST

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To: pirasa2 who wrote (238672)8/13/2007 2:30:41 PM
From: Joe NYCRead Replies (1) of 275872
 
pirasa,

Would a Brisbane with 2 * 8 MB L2 cache attain IPC parity with the C2D ? :)

ZRAM will more likely be implemented as L3. One reason is that it is probably not as fast as SRAM. Also, implementing it as L2 would mean that the core would have to be redesigned.

Much more likely is that it will at some point appear in Barcelona L3. Swapping SRAM for ZRAM in L3 would not involve touching Barcelona cores.

But looking at the roadmap, there is nothing incorporating ZRAM as far as I can tell. The 6MB L3 (Shanghai?) on 45nm is very likely SRAM. And that is in middle of 2008. So when will the ZRAM show up? The best case scenario is that they may be doing a parallel development (on 45nm, with Shanghai), but even that is questionable.

Joe
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