"There will need to be RTL changes"
To the core? Why?
"pipeline changes in the cache controller logic"
Why?
"transistor changes"
Maybe. But not for the processor.
"process changes"
You better tell the people who are marketing the ZRAM technology. They claim otherwise.
" backend changes, etc."
I think you are just justing whatever comes to mind without thinking about it.
"Yeah, but what are the chances of that?"
It would depend on the design goals, now wouldn't it?
"Z-RAM is a fundamentally different technology."
Not so sure it is fundamentally different. It just takes advantage of an existing problem when using SOI.
"The control logic is going to be completely different."
And those differences are restricted to the L3 cache. Not sure what your problem with this is.
"By the way, have you figured out where you are going to put the tags?"
Umm, it is on the L3. Where else would it be? The L3 is designed as a separate module, to the processor it might as well be memory or the cache in another processor. By attaching to the crossbar, it decouples the L3 from the core.
"he space required for 30MB of cache is quite different than the space needed for 6MB of cache. Address lookup will take longer, too."
What is the point you are trying to make here? The memory cell size is different. So the space requirements are different. Granted. So what is the point?
"Redesigning the Shanghai core will require a lot of man power that could be better suited for projects that actually make contribute to revenue, rather than practice."
Correct. In fact, I made this point. I went even further, I pointed out it probably wouldn't make any sense to change the cache policy to inclusive from exclusive to enable ZRAM in Shanghai. But, you are claiming it would take more changes for that, and you haven't made a case for it but to wave your hands and spout buzz words. That may fly on the Intel board, but... |
