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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 230.23-4.3%3:59 PM EST

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To: Joe NYC who wrote (238921)8/16/2007 2:58:30 PM
From: wbmwRead Replies (3) of 275872
 
Re: Core has to be re-validated? That is very far fetched. The processor has to be validated, but the core does not need to be re-validated.

Where did I say that the core had to be revalidated *by itself*. Obviously, you would revalidate the entire device, and test the core behavior *with* the new cache controller attached.

Just to spell it out for everyone, Z-RAM in an existing design would most likely require:

- New cache cell design (at the very least!)
- Likely process tweaks or modifications
- Reliability verification, additional parity or hardened latches may be required on an unproven design
- Performance simulation to determine best size and design parameters

- New micro-architecture for the cache controller (to compensate for different read and write timings, which are vastly different than SRAM)
-- which would necessitate new RTL for the cache controller
-- which would necessitate new validation of the cache controller and cosim validation with the core and cache controller
-- May require fixing of bugs or design flaws inside of the core that have only been exposed due to specific design parameters of new technology (I have personally seen this before!).

- New top level RTL (ok, this is trivial)
-- which would necessitate full chip validation
-- and which would also necessitate relaying out the design, redoing the masks, and taping out almost every metal layer and poly over again
-- and quite possible necessitate additional steppings to iterate on the design and fix bugs on a technology that has not yet been proven in any AMD design before it.

Taken altogether, this is a heavy modification of the design and requires a lot of additional work.

And that's it. If anyone wants to question whether this is FUD or smoke, I have no comment. There is no justification or motive to twist the facts here, as it has no implication to AMD's current roadmap, does not badmouth anything AMD is doing, does not forecast any doom or gloom in any possible way. It merely serves to represent that changing the fundamental cache architecture to a brand new and unproven technology is not a simple modification that can be done in a single stepping with a trivial design staff.

But as usual, it's hard to even point out the obvious when everyone reading this forum is looking for an Intellebee to attack....
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