wbmw,
Just to spell it out for everyone, Z-RAM in an existing design would most likely require:
- New cache cell design (at the very least!)
Of course
- Likely process tweaks or modifications
The claim is that it is minimal
- Reliability verification, additional parity or hardened latches may be required on an unproven design
That may be ongoing as we speak, in test chips. This is where the hang-up is currently, IMO.
- Performance simulation to determine best size and design parameters
That's not really a big deal, IMO. Caches have been around for decades, and the issues are pretty much settled. Additionally, L3 in Barcelona is a complete black box, its effects easily simulated. Well, easily compared to other challenges in core, memory controller, crossbar design.
...-- and quite possible necessitate additional steppings to iterate on the design and fix bugs on a technology that has not yet been proven in any AMD design before it.
First of all, I don't know the first thing about designing microprocessors, but it seems to me that a logical way to go about this is to build test modules (standalone, without processor) and fiddling with that. As I said, it is a black box, so the issuing requests / testing results and timing them, testing reliability should not be all that difficult to test.
This is, IMO, what AMD is doing currently, and it is kind of like inventing a wheel, since nobody has any experience with this technology, AMD is doing it first, which is why it is taking a while,
Joe |
