SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 230.23-4.3%3:59 PM EST
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: wbmw who wrote (238932)8/21/2007 1:45:32 PM
From: TimFRead Replies (1) of 275872
 
- New micro-architecture for the cache controller (to compensate for different read and write timings, which are vastly different than SRAM)

Why? LV3 is off of the cross bar, wouldn't it work like any other LV3, or main memory, or access from other processors, its just a request over the crossbar that comes back quicker than a main memory request (but slower than a SRAM LV3 request).
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  

HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News