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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 236.78-6.1%3:59 PM EST

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To: graphicsguru who wrote (239537)8/29/2007 2:05:57 PM
From: fastpathguruRead Replies (2) of 275872
 
The result is *much* better latency at the cost of *much* greater complexity.

Maybe it's not SO bad... The overall requirements would be: Save the state of the program at the moment the speculative read is "filled" and used (equivalent to an "onboard context switch", worst case), and prevent any potentially tainted results from leaking back out before the cache line is "validated."

The "context save" will just suck up processor cycles that would otherwise be waiting for the read to fill anyways.

"Rollback" consists of simply "context switching" back, and restarting with the by-now-correctly-filled cache line and read results.

Not so crazy.

fpg
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