SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 236.78-6.1%3:59 PM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: graphicsguru who wrote (239537)8/29/2007 2:18:08 PM
From: TenchusatsuRead Replies (1) of 275872
 
GG, > Understand that CSI is "speculative cache coherency." It's game changing.

Huh? That's up to the requesting processor, NOT its bus cluster. If the core wants to speculatively use a cacheline before it is fully snooped, that's up to the core. If the snoop turns out not to be clean, then it's up to the core to undo everything it speculatively executed.

That is independent of CSI.

> I believe that AMD has been right for these many years. "It's all about latency."

It's not like Intel didn't know this. Ever since the Rambus fiasco, Intel has learned about the importance of latency.

Hence the need for large caches on Intel processors, for instance. The best way to reduce latency is not to go outside the processor in the first place.

Tenchusatsu
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext