The New (Profitable) Ramtron Message Board

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : The New (Profitable) Ramtron

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next

From: sleupendriewer	10/21/2007 6:28:47 AM
	Read Replies (1) of 647

I did a little bit comapritve research on simtek and ramtron - one presetation that i found is from simtek and in parts quite interesting to interprete : easytronic.de on the one hand side they argue correctly that fram is a little bit slower than their backed sram solution - but I don't like it that they compare to the 1MBit fram-device out of the fujitsu-process which is realy - as one might see from the figures "trimmed" - if they would take the figures (which were of course not available at that time) from the 2/4MBit devices it would look much better. they leave out also that by burst writing in practice the slight timing advantage is vanishing - imo. it becomes also clear that the 4MBit device seems to consume less energy than MRAM but much more than fram. lastly it is interesting to take a look at the floorplan - I assume that this is the floorplan of the 1MBit in the 0.25 um process and that the numbers in brackets are dimension in um (could be aso in mil - but I realy hope that this is not the case for smtk ;)) in this way we can calculate the area per cell (including utilization) : area seems so be artound 7x3.5 mm (only for the cells - additional logic and analog circuitry for volatage generation not included - this adds 10-20% area) so "raw" cell area in the 0.25um process is around 24.5 um^2 - this is 3 times more than the 8.8 um^2 for a fram cell in the 0.35 um fujitsu process. if we assume that they can shrink it by for the 130nm process than we and up around 6 um^2 - even if utilization should be bad and just around 50% than we will still have cell area of 3 um^2 - compared to 0.7 um^2 for fram in 130nm - and in comparision to fram we still have some additional area needed for charge-pumps etc ... well - if someone likes to review criticaly these crude numbers - don't hesitate to do so - but I would assume that there is an eveident area advantage for fram. my further assumption is that theprocessing costs for the sonos process in order to integrate additional nonvolaitle backup and the two additional mask steps for fram might add comparable costs to the standard-cmos-process - so after all fram might have due to less area clear cost advantage ... my 2 cents - if I'm wrong in one way or the other - let me know ...

Report TOU Violation

Share This Post

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next