die sizes ...
well, there is something interesting I came across :
recently chipworks published in their blog that the die size of the 4MBit is around 17.4 mm^2 - that was a little bit to my surprise because I had somewhere in my head that the 8Mbit device in this (2005)-IEEE-paper "An 8Mb 1T1C Ferroelectric Memory With Zero Cancellation and Micro-Granularity Redundancy
Jarrod Eliason, Sudhir Madan*, Hugh McAdams*, Glen Fox, Ted Moise*, Changgui Lin, Kurt Schwartz, Jim Gallia*,
Edwin Jabillo, Bill Kraus, Scott Summerfelt*, IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE" was 16.8 mm^2 ...
when you now take a look at the die photo of chipworks ( chipworks.com ) and the one in the paper (you can find the paper easily in IEEE xplore) and compare the major block structures - also of the memory they match interestingly well (besides that there are some additional pad-structures in the IEEE-die, ...)
so I'm, wondering a little - how can the 8MBit part they published 2005 and the 4MBit they are selling right now have so much in common - even similar die size ...
Of course the question comes up if the 4MBit-part they sell right now is realy a 8Mbit part that is just for some purposes reduced to 4Mbit - and if yield or whatever is up - they might go to 8Mbit ...
In the paper the block structure is described a two(!) 4MBit blocks with 8sections of 512kb (each block) with 16 sections. So one(!) block ressembles what is given in the datasheet of the FM22L16.
As the die photo of chipworks (which is also similar to the one that ramtron publishes) suggests that there are still two blocks on the die - the assumption (!) is near that they fab both blocks but use for the part only one block ...
I think this would be an interesting "thing" - because by this they could bring very fast lateron a 8Mbit-version - with no additional costs to what they market right now as 4MBit. (and if in the 2Mbit-device we have a similar situation this might migrate to 4Mbit lateron ...)
I realy don't understand right now the reason for this approach - because in the paper they describe 3 quite elaborated ways to cope with bit cell errors - which are quite interwesting to read - and which may make the difference to other fram-cell-structures - like samsungs for example which now have approached just double the die area of the 4Mbit device - but for 64 Mbit !!! - in a recent research paper - and this is done in a 130nm-process !!! (so : there is plenty of room at the bottom for fram - even at the 130nm node - if one wants to push it in a certain way - of course there might be some tradeoffs ...)
anyway : what I wnated to point out is that there is some surpising (at least to me) similarity between the 8Mbit device TI/Ramtron published 2005 and the reengineered device chipworks examined - the question is : how to interprete this for the future ... |
