Hi Pam,
Good to see we're on the same page now for as far as cell sizes are concerned for Mirrorbit Quad and 2b/c NAND (Quad being ~ half a process node denser). This rather obviously does not mean that Quad competes with mainstream NAND markets, but rather that it could well be cost competitive with Mirrorbit/ORNAND MCP's and in some small niche markets.
I saw you took the diagram from Spansion that I referenced and added the newly announced 3b/c NAND from Tosh. Could you please provide the exact data point(s?) you used to draw the line? I could use some hard data here because I've got a bit of a dilemma with it as it is not in line with a previous statement I read that said those chips would only be some 20% denser than 2b/c NAND (hope I recall that one correctly). If what I think I read is correct then the new line showing density of 3b/c Tosh NAND should be more or less the same as that of Mirrorbit Quad at the same process node). I think ideal scaling for 3b/c Tosh NAND compared to 2b/c Tosh NAND (33%) is difficult because of added error correction logic and possibly more elaborate voltage sensing mechanisms too.
Separately two small details: It's possible that 3b/c NAND will never be transitioned as fast as as 2b/c NAND to the newer process nodes. Also it's possible that if 2b/c makes it finally to 30nm using floating gate, that 3b/c gets stuck e.g. half a process node earlier.
re: Well, you would be fairly close if you had compared 65nm Quadbit with 56nm NAND MLC (instead of 50nm)
I already had changed my first estimate (65nm Quad ~ 50nm NAND) that was indeed a bit off, to 65nm Quad ~ 55nm NAND in the post where I provided the board with the Spansion diagram (the one you then used to add 3b/c Tosh NAND). Should I really have mentioned that I prefer Spansion's direct data over my own earlier estimate based on obviously less direct data? Ref: Message 24185508
re: Toshiba's run at high 90's! Thanks to ECC which makes even dies with errors economically useful as lower density dies!
Is this hard data (the high 90's)? Hopefully you've got the details to which process and what die this is applicable? And perhaps what kind of yield (line/wafer sort/final test) it is?
BTW, ECC used in NAND flash makes makes most dies with a not too high amount of bit errors useful at the same (not lower) max density that they were designed for.
re: Spansion's highest density for ORNAND is just 4Gb! Do you know if it is a monolithic chip or a dual-die or a quad-die?
4Gb is dual die currently.
re: Do you know approximately how much time it takes for Spansion's ORNAND to be manufactured from start to a finish?
I'm not sure. Really don't have time to look it up (sorry). Does anyone here know?
re: As I indicated earlier, it will be really hard for Spansion to catch-up in data storage. NAND players are moving extremely fast and they have the resources.
- Spansion is imo ok for all NOR containing MCP's, excluding those that use very high amounts of NAND, but including those with a reasonable amount of ORNAND.
- Spansion has the resources imo for a not too steep ramp of SP1 on 65nm and later migration to 45nm in that fab provided that prices don't crash as they did in H1'07 (a quite big but not unreasonable provision).
- Spansion's portfolio has a rather broad line of flash products including a quite reasonable amount of value added solutions that go quite a bit beyond a pure flash chip package. Based on their portfolio, roadmap, technology, and market position they stand a very good chance against all other NOR flash companies, specifically including Numonyx.
There are obviously a good amount of people that don't agree with my overall conclusion that Spansion will continue to gain share and reach op profit during 2008. I'm evaluating it again (cash burn specifically). It's obviously high risk (see current share price), but possibly high return too.
Regards,
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