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Technology Stocks : Spansion Inc.

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Apr 16 5:00 PM EST

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To: Rink who wrote (2954)	1/7/2008 10:54:40 AM
From: Pam	Read Replies (1) of 4590

Could you please provide the exact data point(s?) you used to draw the line? I could use some hard data here because I've got a bit of a dilemma with it as it is not in line with a previous statement I read that said those chips would only be some 20% denser than 2b/c NAND (hope I recall that one correctly). If what I think I read is correct then the new line showing density of 3b/c Tosh NAND should be more or less the same as that of Mirrorbit Quad at the same process node). I think ideal scaling for 3b/c Tosh NAND compared to 2b/c Tosh NAND (33%) is difficult because of added error correction logic and possibly more elaborate voltage sensing mechanisms too. I do not have any hard data and the line I drew is my estimate (take it with a huge grain of salt.) Ideally, it should have been about 1/2 (keep in mind the log scale) of the distance between SLC and MLC lines below the 2 b/c line but I just drew one 1/3 below because it seems there is some penalty as they increase the bits/cell. See article below. It has some info about 15% increase in die size for a 16Gb 4 b/c prototype by Toshiba at 70nm vs. a 16Gb die size with 2 b/c at the same node. Separately two small details: It's possible that 3b/c NAND will never be transitioned as fast as as 2b/c NAND to the newer process nodes. Also it's possible that if 2b/c makes it finally to 30nm using floating gate, that 3b/c gets stuck e.g. half a process node earlier. Not so fast. Read this for more info. Message 24188182 re: Toshiba's run at high 90's! Thanks to ECC which makes even dies with errors economically useful as lower density dies! Is this hard data (the high 90's)? Hopefully you've got the details to which process and what die this is applicable? And perhaps what kind of yield (line/wafer sort/final test) it is? BTW, ECC used in NAND flash makes makes most dies with a not too high amount of bit errors useful at the same (not lower) max density that they were designed for. You will not find any hard data. It is not that unusual for NAND makers to have raw yields of acceptable dies at correct capacity in low 90's. Using slightly defective dies at lower capacities makes the yield go up even higher.

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