Pam, Thanks for the informative article + it seems we're reasonably in line with the data at least.
From your article: Toshiba's 4b/c NAND adds 15% die size due to additional ECC, and possibly sensing technology (3b/c adds unknown amount of die size; could it possibly be that ECC circuitry for 4b/c was implemented with 3b/c already? -- alternatively I remembered the 15% expansion due to ECC for 4b/c and mixed it up with 3b/c...). Write are speeds down to 1Mb/s for 4b/c although this could possibly improve (write speeds of 3b/c??).
OK, I do not find any data in that article that would indicate that 3b/c will be migrated as fast to newer nodes as 2b/c, but the basic process roadmap looks impressive anyway:
Overview of Tosh's process roadmap:
2007: 56nm, immersion, 2b/c, 16Gb/chip
2008: 43nm, immersion, high-k, transition starts early '08, 2-3b/c, 32-48Gb/chip
2010: 3xnm, immersion, better high-k, FUSI (fully silicided), double patterning, 2-4b/c, 64-128Gb/chip
201x: 2xnm, abandon floating gate for charge trapping
201x: 1xnm, 3D structure based on charge trap or cross-point junctions
I'm still seeing the transition slowing bit by bit (maybe even after 43nm already if above 30nm generation turns out to be a bit higher than 30nm like e.g. ~35nm) and costs per mm2 increasing exponentially too. Not betting on that but:
- With 56nm they added immersion
- With 43nm high-k
- With 3xnm better high-k + FUSI + double patterning.
Granted, 43nm to 30nm (and a bit?) would be a full node, while from 56nm to 43nm isn't, but still it's a lot of process technology to add for 3xnm. 3xnm doesn't come cheap.
Tx, regards,
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