Seifun had a small positive income. I am not sure how it would turn to large negative income once under Spansion umbrella. Part of the revenue that made Saifun profitable was revenue from Spansion, so any loss of revenue of Saifun offsets loss of expense for Spansion.
The R&D expense of Seifun - Spansion already paid a portion of it - through license payment to Seifun. Now, instead, Spansion will make these payments in form of payroll checks.
Saifun had an Operating loss last Q but you are right about what you said. I looked at the loss in a rush without paying attention to where it came from. That loss happened because of merger related expenses. So, adding Saifun's payroll is a wash with Spansion's L&R payments to Saifun before merger. Still, revenues need to grow for Spansion to be able to leverage higher R&D expenses, which would be somewhat sticky. If their technology is as good as they claim, they should be able to find licensees which could help, the way it is helping Sandisk.
What will affect the road to profitability for Spansion (to a much greater expense) is the depreciation charges for SP1, which will start to hit the P&L statement. I think we will hear a lot in terms of EBIDTA.
The key is GM expansion which currently stands at 18% Without an improvement in GMs Spansion, will not survive for too long. When 65nm goes into production, a clearer picture will emerge on their GM front. They also need to gain market share from others so that others lose economies of scale.
If you have paid attention to Spansion over last 2 to 3 years, Spansion process transitions have been actually faster than market. Well, you may say: it is easy when you are far behind, and it is true to some extend. But the fact is that Spansion is at 65nm now, 65nm 4-bit per cell is sampling, 45nm is running in R&D fab and it is supposed to enter production in 2H 2008.
A big news for Q1 / Q2 would be if Spansion announces sampling of 45nm Mirrorbit, which would be a confidence boost that 45nm process technology is on track.
Well, it remains to be seen how successful 65nm transition will be. Production hasn't started yet, but hopefully it will happen soon.
Now, 45nm for Spansion is a bit of a wild card because, apparently, it is the first node to use immersion lithography, but if Spansion executes and is at 45nm before the end of 2008, I see nearly a process technology node parity. It may not turn out that way, but it is certainly a scenario that is not outside of realm of posibilities. Another thing to keep in mind is that Spansion has already mastered charge trapping, and has a whole bunch of patents in the area (now with Seifun, even more). The NAND players will not only have to master something that Spansion is already at volume production with, the NAND players will have to work around Spansion patents to do so - or enter a licensing agreement.
Transition with every node gets difficult. Spansion's 65nm production has not even started yet and it is a bit premature to think about 45nm! IMFT tried dry lithography with 50nm NAND and had to move to immersion. Samsung has had their fair share of troubles with transitions to finer nodes, especially with MLC NAND. So we will have to wait and see how smoothly 65nm transition happens for Spansion and what kind of yields they are able to get. In my opinion, NOR and NAND flash are two different technologies, meant for two different set of applications. It is unfair to compare the two and somewhat useless. But you comments about Spansion's experience with CTF and lack of one with Immersion Lithography and exactly the opposite for NAND players, are valid and well taken.
I would not dismiss out of hand the possibility that Spansion will close the gap, or even get ahead in silicon die area / bit. But Spansion will still be processing 1/10 to 1/20 of the 300mm wafers, so an absolute cost per bit will be a challenge for Spansion - unless everyone else trips up during their transition to charge trapping.
I am not sure about this. I am not too familiar with Spansion's die sizes but the one they showed in 2007 AD presentation slides had 10mm2 die for a 32Mb die at 90nm (not sure if it was SBC or MBC). At 65nm, one would expect Spansion to deliver 64Mb in the same die size. If I extrapolate this, it would approximately take 160mm2 of silicon to get to 1Gb at 65nm and now if I assume that this is using SBC, with a Quadbit architecture, I would get 4Gb in 160mm2 and that is no match to Toshiba/Sandisk/Samsung's 8Gb on 56/51nm with a die size of under 100mm2! And they are about to move into production to 43nm and also 3 b/c shortly, which widens the gap further! In semiconductors, a couple of Q's lead in a competitive market will result in losses for the one behind in technology! Spansion's competition is with Numonyx, Samsung, etc. in NOR and not with NAND vendors!
I am not either, but I very much we are going to find out anytime soon. One reason is that largest dies Spansion produces aer still a fraction of die sizes of NAND players - generally 20 to 50 mm^2, where NAND players go to 100s of mm^2.
Basically, as I said you can't just look at die sizes without looking at the capacity it offers! You are right, NAND manufactures have their die sizes in the range of 98mm2 to 170mm2 but they offer a lot more capacity and definitely are more denser than 20 to 50mm2 dies from Spansion. Toshiba 170mm2 die (approx.) offers 16Gb of capacity at 56nm!
Second reason is that Spansion has no incentive to even produce these size dies anytime soon, and has no incentive to fight loosing battle head to head with NAND players.
Spansion's best chances are in devices that need low densities for boot purposes and small amounts for data storage. As storage requirements increase, they will not be able to compete with NAND players.
Spansion competition is mainly Numonyx, and between the 2 of them, Spansion occuppies low to mainstream of the market, Numonyx occuppies mainstream to high end. So a much more pressing goal for Spansion is to displace Numonyx from the high end of the cell phone market occuppied by NOR players. so there is no point in producing 16Gb densities in 2008. Spansion is currently not in any market that has demand for densities this high.
Exactly! NOR business is stagnant and the only way to survive is to steal market share from a weaker player and achieve growth for yourself.
I see now that you are counting 56nm half node as a node, which clarifies a bit your earlier comment that NAND players are 2 nodes ahead - which seemed a bit far fetched.
So, yes, I agree that Spansion is 1 node behind (which you count as 2) but the gap widening heavily depends on Spansion stumbling on 45nm.
Well, I should have used the word "transitions" instead of nodes;-) There are times when these companies move half a node and at other times they move a full node, all depending on availability of appropriate tool sets, besides other things. Spansion has also done "half" nodes with 110nm to 90nm and some before that.
So yeah, one can have a higher confidence that Tosh will enter production at 43nm ahead of Spansion, and that chances of Toshiba stumbling are much lower. So while the confidence level, and probability to stumble (at 45nm) is higher for Spansion (production is still nearly a year away), you can't just count it as something that is given.
I am not doubting Spansion's ability to do a 45nm transition, but I think it will go into production sometime in 2009 not in 2008.
And going from 45nm further is supposed to put floating gate players in the bind, so you can't just count on that not happening...
Going to 3xnm from 46nm will be a challenge with FG but hopefully they will be able do it one more time. IMFT is supposedly working at 35nm, not sure whether it is FG or CTF. |
