[edited] NOR-NAND DIE size
Some hard facts in that link:
128.100.10.145
(linked from BR@AMD-WO -> thx)
Page 65:
23.2 A 4b/Cell 8Gb NROM Data-Storage Memory with Enhanced Write Performance
1Saifun Semiconductor, Netanya, Israel
2SMIC, Shanghai, China
A 155mm2 8Gb data-storage memory based on a 4b/cell nitride ROM (NROM) in 90nm
CMOS is introduced. The design features a programming method in which all levels are
programmed in parallel and an approach for regulating erase current, resulting in a
large improvement of write performance. A read scheme together with a datascrambling
method is implemented to allow better immunity to data-pattern-related
array effects and to minimize the cumulative program-erase cycling effect.
So, QuadBit-MB DIE 8Gb is on 90nm = 155m^2. My assumption:
8Gb DIE Quad 65nm = 0,55-0,6 x 155 = 85-93 mm^2
8Gb DIE Quad 45nm = 0,55 x 90 = 50 mm^2
So, now comes the main competition (NAND), which some people
believe are so much in front! It looks amazingly good for
SPSN. Why?
Page 66:
A 120mm2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology
What does this show to us?
SPSN NOR 8Gb Quad 45nm = 50mm^2
SPSN NOR 16GB Quad 45nm = 100mm^2
Toshiba NAND 4-MLC 16Gb 43nm = 120mm^2
Do I have to say more?
edit:
Just to not look so much into the future!
SPSN NOR 8Gb Quad 65nm = 90mm^2
Toshiba NAND 4-MLC 8Gb 43nm = 60mm^2
Toshiba NAND 4-MLC 8Gb 51-55nm = 90mm^2
So, when I use the current NAND node (5x nm) on 300mm and when
I use Quad from Spansion on 65nm, the DIE size is roughly
EQUAL, even when we give Spansion 65nm!!! So, when SPSN
uses the same node, they are "way" in front with Quad.
BUGGI |
