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Technology Stocks : Advanced Micro Devices - Moderated (AMD)

AMD 214.18

-0.5%

Dec 31 3:59 PM EST

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To: combjelly who wrote (247819)	2/14/2008 4:14:12 PM
From: wbmw	Read Replies (3) of 275872

Re: The PIII had 12 stages in order and 2 out of order. Better tell Intel to update their slides. They claimed 10 stages in their comparison foils with Pentium 4. anandtech.com The K7 had a 10 stage integer and 15 stage floating point pipeline. This was the best diagram I could find to illustrate it: cs.utah.edu So they each had an integer pipeline depth of 10, but that does not invalidate my point. Intel designed the P6 pipeline in 1995 for their 0.6u process. Many things change between that and the 0.18u Pentium III, and a repipelining might have certainly contributed to enabling higher clock frequencies, even while keeping the number of critical stages the same. Many claimed that AMD designed the K7 core for their 0.18u process, even though they initially launched it at 0.25u. But unarguably, it had a better balanced pipeline for driving to higher frequencies.

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