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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 214.96+5.5%Nov 24 3:59 PM EST
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To: pgerassi who wrote (248677)3/12/2008 3:28:26 PM
From: chipguyRead Replies (1) of 275872
 
It has 16 spare rows per 256 line array, but just two columns spare in each 72 bit wide array

LOL, I guess this an example of one of those "rare" designs
with both row and column redundancy. And it's a 16 KB first
level cache array macro no less.

No doubt as you get into the hundreds of KB and megabyte
range and start occupying some serious die area having
both row and column redundancy becomes even rarer. :-P
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