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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 195.33-9.1%10:16 AM EST
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To: chipguy who wrote (248679)3/12/2008 4:45:25 PM
From: pgerassiRead Replies (1) of 275872
 
Chipguy:

If you would have read the document, row spares and column spares become lower with bigger macros, not more of them. They may recover a bad row or a bad column, but they don't recover two in the same set. Of course L1 caches have more redundancy, they are more critical as the loss of L1D cache size and the chip is no longer saleable. Losing L2 and L3 are less critical. As the criticality of the cache goes down, so does the redundancy. But you should know that, if you design on die memories. This is what shoots down your credibility.

You may design fine memory macros, but the big picture stuff seems to escape you.

It isn't the number of spares, but the area they cover and the fact that 1.97MB of cache is fused down to 1MB of cache at the very least. As for yields, even allowing for 1% of any given section to be bad, having 64 of them increases the chance of any one section being bad to 47%. The chance of 32 of the sections being good in a half of the cache are 92%. That makes for 53% having 2MB of cache good, 39% having 1MB of cache good. This is reinforced by having fully independent L2 cache halves. And it shows how designing for half of L2 cache or any individual cores to be disabled, increases effective "yield" in terms of revenue per wafer.

Pete
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