Patents
I looked at bit through the SPSN/SFUN patents filled in the
US. I couldn't look for a long time, so I advice everyone
to take some time here:
patft.uspto.gov
Interesting, that SPSN is doing some organic/polymer stuff
too. I have found these patents interesting.
patft.uspto.gov
"
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The present invention provides a dual-level flash memory cell design that can yield 3 or more bits per transistor, that is scalable, and that can be operated with relatively simple peripheral circuitry. The memory cell employs multiple dielectric layers and poly layers so that more bits can be stored in the cell than with conventional configurations. Additionally, the multiple layers can facilitate scaling of the memory cell to higher densities than conventional configurations.
The dual-level memory cell stores two lower bits in a first level and stores an upper bit in a second level. The lower bits are programmed, erased and read by alternate modes of operation wherein active regions operate as source and drain, and then drain and source. The upper bit is programmed and erased independent of the lower bits. However, reading of the upper bit depends upon read values of the lower bits. Additional levels are employed to store more than 3 bits of information.
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I don't know, what this will mean for manufactoring, but
if they could do 3,4,5,6 bits with 2 voltage levels, this
seems to me amazing. Just look for images here:
patimg1.uspto.gov
A BIST patent, which explain the advantage more in detail:
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Full built-in self test (BIST) refers to the on-chip capability to execute all of the tests normally done with a conventional wafersort tester. With BIST, all die on a wafer may be given the "test" command at the same time, enabling each die to "test itself" concurrently without further tester intervention. Since all die on the wafer are tested generally in parallel, the test time is reduced to the time that it takes approximately to test one die, as compared to conventional wafersort testing wherein die are tested one group at a time (e.g., 16, 32, etc. die/group). This dramatic decrease in testing time reduces the test cost greatly. Accordingly, fewer testers are needed to test a given number of wafers, and wafer lots can be processed in considerably less time. All of the tests, which are normally included as part of the wafersort testing can be included in the BIST test flow.
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"
patft.uspto.gov
Faster erase programming:
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Although reducing user's data retention density, the above method has been found to provide improved programming speeds by about 4 times or more over conventional programming of the 2 bits in dual-bit flash, or the single bit of NAND flash.
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patft.uspto.gov
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