Michel and thread,
Business Wire
RAMBUS DETAILS NEXT-GENERATION, HIGH-SPEED MEMORY INTERFACE
SAN JOSE, Calif.--(BUSINESS WIRE)--Oct. 15, 1997--
Headed for main memory, consumer electronics and communications systems, Direct Rambus(TM) technology sustains 1.5 Gbytes/sec per device and supports multiple DRAM densities
Rambus Inc. will today disclose technical details of its Direct Rambus high-speed memory interface here at the 10th annual Microprocessor Forum. The new technology will enable the DRAM industry's highest level of performance to date - 1.5 gigabytes per second (Gbytes/sec) of sustained bandwidth from a single device. In addition, the technology will span multiple generations of DRAM devices - from 32-megabit to 1-gigabit densities. As a result, Direct Rambus technology gives original equipment manufacturers a stable memory interface for the next five years.
"For the past 10 years, processor performance has doubled every 18 months, but memory performance has not kept pace. In effect, memory has become the principal bottleneck to system performance," said Geoff Tate, president and CEO of Rambus Inc. "The goal of the Direct Rambus program is to break the memory bottleneck by delivering
breakthrough performance at affordable system costs for a wide range
of applications. With the help of Intel and our other partners, we
believe we are well on our way to meeting this goal."
The Direct Rambus interface achieves its unprecedented performance
through electrical and architectural extensions to currently available Rambus technology. By increasing bus frequency some 33% to 800 MHz as well as doubling data-bus width to two bytes (16 bits), Direct RDRAM devices will be able to achieve 1.6 Gbytes/sec peak transfer rates from a single chip. For highest-performing memory systems, a 64-bit datapath using four Rambus Channels yields 6.4 Gbytes/sec of performance. To achieve 95% efficiency for the improved Rambus protocol, the architecture defines separate row, column and data buses to greatly increase control bandwidth. And a pipelined memory architecture supports multiple, simultaneous interleaved transactions. For example, a single Direct RDRAM device permits four interleaved memory operations and multiple Direct RDRAM devices can support up to eight simultaneous operations.
Like existing Rambus technology currently shipping in PCs and consumer electronics systems, the Direct Rambus technology will support high system performance at low system costs. Direct Rambus DRAM (Direct RDRAM(TM)) devices use conventional DRAM cores, fabrication techniques and packaging. In addition, Direct Rambus memory modules, called RIMM(TM) modules, use standard industry assemblies similar to those of today's dual in-line memory modules.
Further, for PC main memory, a Direct Rambus memory system will fit
within the same physical, power and thermal profiles of a similarly
configured 100-MHz synchronous DRAM memory system.
Developed in conjunction with Intel Corp. and in cooperation with other Rambus semiconductor partners, the Direct Rambus technology is
gaining broad industry support. Intel Corp. late last year disclosed its plan to use Direct Rambus technology for PC main memory components that are expected to begin shipping in 1999. More than a dozen DRAM companies, including the world's top 10 DRAM makers, have announced their intention to develop Direct RDRAM products. And in September, 18 companies representing the leaders in system-memory implementation products - including memory modules, connectors, clock chips and test systems - announced their intention to support Direct Rambus technology. Planned applications include computer system memory, multimedia and graphics memory, communications system memory and consumer electronics memory.
Volume production of Direct RDRAM devices from Rambus licensees is
expected to begin in 1999.
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