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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 223.44+4.3%3:59 PM EST

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To: mas_ who wrote (252875)6/5/2008 2:51:27 PM
From: Elmer PhudRead Replies (1) of 275872
 
Sorry but the 4-11-39 cycles L1/L2/L3 is what it is, an inferior cache structure to Penryn's 3-15 L1/L2 up to 6MB.

mas, I don't have all the facts but clearly neither do you. To think that you can fully understand the issue by simply tossing up numbers like 4-11-39 is rather presumptuous on your part. I find it hard to believe that Intel would introduce a new architecture with a worst cache scheme. It doesn't stand to reason. With the IMC it is clear that the average memory access, whether to SDRAM or one of the levels of cache will be greatly enhanced both in terms of latency and bandwidth. That's what really matters.
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