Advanced Micro Devices - Moderated (AMD) Message Board

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD)

AMD 223.44

+4.3%

Jan 2 3:59 PM EST

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next

To: dougSF30 who wrote (252878)	6/5/2008 3:34:50 PM
From: mas_	Read Replies (1) of 275872

You are confusing main-memory prefetching with inter-level cache fetching when you talk about disabling prefetching for certain FSB-constrained benchmarks on Penryn. 'inter-level cache fetching' is a complete figment of your imagination. Please point me to a technical description of this made up BS. prefetching does not "only work for non-random patterns". It does not "work" or "not work", but rather works better the more uniform the access pattern is. BS. It is a hindrance with random memory accesses because it fills your cache up with data that isn't used and only has to be evicted which is why it is disabled in many benchmarks. spec.org Disabled 'Hardware Prefetcher' in BIOS Disabled 'Adjacent Cache Line Prefetch' in BIOS spec.org Bios settings: Hardware Prefetcher: Disabled Adjacent Sector Prefetch: Disabled The 'numbers' are derived from an industry-standard benchmark, it showed what happened when the rubber hit the road.

Report TOU Violation

Share This Post

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next