And speaking of "opening shots"...
Remember this news from AIST regarding development of a feasible 3D, ferroelectric, 1T-FRAM, w/10yr endurance and 100M more access cycles published May 19?
Message 24707216
Then picked up by the trade press June 27?
electronicsweekly.com
Now... roughly two months later... look who's talking 3D transistors:
Qimonda, Siltronic research next-gen transistors
Christoph Hammerschmidt
EE Times Europe
(07/03/2008 8:55 AM EDT)
MUNICH, Germany — Memory chip maker Qimonda AG and wafer manufacturer Siltronic AG have joined forces to conduct basic research for future transistor architectures. The research focuses on three-dimensional transistors which will enable smaller geometries.
The research activities are part of the SIGMADT research project which is funded by the German federal research ministry with €6.5 million (about $10.2 million). With the funding, the ministry intends to strengthen the Saxonian semiconductor industry area around Dresden and Freiberg, where Wacker Chemie AG subsidiary Siltronic runs a wafer production.
For the semiconductor generation after the next one, it becomes evident that three-dimensional transistors replace today's two-dimensional architectures, a Qimonda spokesperson explained. "These architectures are not entirely new; they have been introduced at the IEDM in 2005 and 2007," she said. Besides smaller geometries, these transistors also use less power and sport higher switching frequencies.
The cooperation with Siltronic aims at finding the set of physical wafer properties that matches best the requirements of three-dimensional transistor manufacturing, a Siltronic spokesperson said. In addition, the research aims at developing manufacturing processes for the wafers to be used to produce 3D-transistors. According to Siltronic, this kind of production requires extremely planar and smooth wafer surfaces.
The research project is scheduled to take about two years.
eetimes.com
$10M is a drop in the proverbial bucket. And developing a preferred wafer spec is a punt compared to the heavy lifting that AIST and others have already done. But in 2 years the DRAM industry (QI's forte) will be ramping 32nm as the bleeding edge process and if planar 1T/1C DRAM cell design is ever going to crap out... it should be painfully obvious by then. So I figure QI's timeline for this project won't have much leeway and it appears they shouldn't need it.
The big question for me is whether it will make any sense to develop a 3D DRAM which is still volatile for the mainstream DRAM market? I guess... like everything else... it will depend upon the price/performance points, but either way I don't see how they'll make a 3D DRAM without using a ferroelectric layer and that will result in ever more $ going to ferroelectric development.
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