Eracer:
Lets first take your obviously biased statement that a 2nd gen 45nm SOI R810 like core, 80:4:4:64:16, (shaders:TFUs:ROPs:memory bits:PCIe lanes) could be just 20mm2. Obviously you don't know about QAD back of the envelope calculations. Lets look at the details leading to this. First any core on Fusion would be sans ODMC, PCIe and any interface (it goes down the existing HT, ODMC and additional NB ones for PCIe which will be outside the core area). Thus the last two numbers above are missing. These tend to be large areas. You can easily see that looking at any Opteron, Athlon64 or Turion dies, especially Barcelona from which Shrike will use Shanghai as a basis.
We know of 4 dies all made on TSMC's 55nm bulk logic process, the R770, R670, RV635 and RV620. The first is 260mm2, the second 192mm2, the third 118mm2 and the fourth 67mm2. he amounts of the above are 800:40:16:256:16, 320:16:16:256:16, 120:8:4:128:16 and 40:4:4:64:16 respectively. Using this we get four equations with 5 unknowns, 20x1+10x2+4x3+4x4+1x5=260, 8x1+4x2+4x3+4x4+1x5=192, 3x1+2x2+1x3+2x4+1x5=118 and 1x1+1x2+1x3+1x4+1x5=67 where x1 is the area of 40 shaders, x2 the area of 4 TFUs, x3 the area of 4 ROPs, x4 the area of 64 memory bits and x5 the area of 16 PCIe lanes and all common portions between the dies. Granted this misses some differences in the R770 compared to the R670 derived designs and leaves out the complexity of the controls on the dies, but it should give some idea of what the sizes are. Yes, it may not solve for all five, but some information can be gleaned.
Trying it nets only that x4 is 39.67mm2. Given that the R620 core on 55nm bulk is 27.33mm2 including the PCIe interface not in the core above. Given that 45nm/55nm squared is ideal scaling, the highest scale factor would be 0.67. Using that we get 18.3mm2 including the 16xPCIe interface which wouldn't likely scale much, but is outside of the core. So it would be well under 10mm2, too small to replace a K10.5 core. Since the R770 uses 10 blocks of 80 shaders each with 4 TFUs on them and is about 101.33mm2 in its core with 16 lane PCIe given that it has 4 64 bit ODMCs. 1/10th of that is 10mm2 prior to scaling. Granted this misses the obvious things that are the same size, UVD2, Tesselation Engine, setup engine, etc. Looking at a die, it is about 20mm2 for all else and 80mm2 for the shaders/TFUs. That puts us again at 28mm2 for 80 shaders (AMD did say they reoptimized the layout and was able to stuff 2.5 times as much into a little more area), which we get 18mm2 at 45nm SOI. Give a little scaling loss due to inefficiencies, and we get the 20mm2 I stated before. Doubling the shaders/TFUs to 160:8:4 gets us to 36mm2 which shrinks to 24mm2 at 45nm SOI. Adding more scaling loss plus some more caches to offset the sharing of memory and we get about the 30mm2 or so of a K10.5 core (core, L1I, L1D and L2 caches). If AMD likes the IGPU being about 1/8th the full blown core as in the RV670 generation, this should work well.
Next your website clearly shows that the platform is Shrike while the CPU/GPU is Swift. Clearly Swift will go into many other platforms, just like was discussed by AMD many times. Here is one such place:
apcug.net
Look at page 23. Clearly Swift uses Phenoms and desktop chipsets as well. Swift is the first Fusion processor with the APU. Shrike is just one of the places it can go. Oops, there goes another of your biased views down in flames.
All the talk is about 8/6 layer Nehalem MBs. I don't see a 4 layer MB discussed. Maybe its a figment of your imagination.
As to Swift not using 2nd gen 45nm SOI, that is what the slides say Swift will use. Not what your imagination hopes will happen.
What he complains is that a 3850 or 4850 GPU is needed for Crysis. That is why he is getting the upgrade. For those games, yes it is needed. But not all DX10 games need the upgrade. As for the chipset heat sinks, the con is for R1.0 boards not the updated R1.1 versions. Both older versions needed aftermarket HSs to keep cool as he stated. That is a problem not with the 780G, but the MB makers decision of what HS(F) to use, where. Many older 780G MBs had too cheap passive HS's on them. Later ones added beefier HSFs. As to overclocking the IGPU, he never stated that one way or the other in the post. Still the option is not unheard of in notebooks. The original AC used DX10.1, if it was available. nVidia, it was claimed, forced removal of that capability in a later patch, because ATI HD3xxx cards killed them in head to head benchmarks, when it was used.
As to your silly claim that DX10.1 is DX9.0c, no current nVidia cards can run full DX10.1 according to their tech people. That has long been a point of contention between AMD/ATI and nVidia. It is not even equal to my claim that DX11 appeared to be complete DX10.1 with all options required. ATI can do that now, nVidia can't. The equivalent is 9.0c to DX10.0. But DX10 requires SM4.0. MS is supposed to finally out DX11 specs at Gamefest 2008. We will have a better idea of what the required features are. Intel seems to have asked MS to pull DX11 from Windows 7 requirements. Rumor is that they agreed. I foresee another i915 type debacle coming.
Pete |
