One wonders why AMD is that slow with introducing their 45nm process given that they employ "standard processing using 193nm immersion tools"? As a matter of fact, DEPD has made considerable progress (sophistication that is), and by now even ASML admits that it is a viable (competitive) approach for logic makers down to 45nm and perhaps even a bit below of that. Producing DRAM or NAND is pretty much all about immersion these days, producing logic is evidently not.
"Intel uses a DEDP (Double Exposure Double Patterned) method to extend its 65nm tools to do a bastardized 45nm process, really a 35nm by 65nm process, trading 9 to 12 months quicker TTM, Time To Market, for lower wafer throughput, due to many more steps, higher required alignment (more time per scan step), more time for each scan because of twice the exposure time, and less yield per wafer again because of those extra steps. All this compared to standard processing using 193nm immersion tools that AMD is using. Yes, Intel gained some back by having a lower die size compared to its 65nm process, but they lost some more by needing even more steps for HiK/MG. All in all, they likely get less good dies per month at equal clean room size than AMD does, even if AMD goes to HiK/MG themselves." |
