Moore's Law takes a backend seat; TSV as next battlefield
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Michael McManus, DIGITIMES, Taipei [Monday 15 September 2008]
While Moore's Law continues to march onward, its pace has slowed. Currently, the semiconductor industry is migrating to 32nm, but the migration to 16nm is not expected to arrive until 2019, meaning that it will take 11-years for the semiconductor industry to advance only two process nodes.
However, industry players are increasingly looking beyond Moore's Law to see how productivity gains can be made without scaling, and currently players in the packaging segment believe that they can help drive the next generation of growth in the industry.
Ho-Ming Tong, chief technical officer at packaging industry leader Advanced Semiconductor Engineering (ASE) recently commented that the packaging industry is actually outpacing growth of the rest of the industry. In contrast to front-end players, the speed in which packaging and testing companies have introduced new solutions is now 4-5x faster than it was 5-10 years ago, Tong pointed out. Packaging and testing advancement is picking up while the rest of the industry is slowing down.
Another challenge facing the industry as growth slows is that development costs for migrating designs to next generation leading-edge processes are enormous and designs are become increasingly complex. Moreover, the market is currently being driven by the consumer electronics industry, where cheaper, smaller and more complex products are not only desired by consumers, but expected as well.
So instead of scaling, semiconductor vendors are turning to more exotic designs or packaging types. The most common method of circumventing scaling that has been to combine technologies into one system on chip (SoC). This is also an area where packaging companies have been creative with their designs, and the industry is seeing increased packaging types that can support multiple chips, including package on package (POP), multi-chip package (MCP) and system in package (SIP).
Historically, these multiple chips would be connected at the board level, but the industry has progressed to the point that maximizing space is a key concern for vendors. Tong pointed out that this trend will continue and that means the packaging and testing industry will see its influence increase, as vendors turn to them for these 3D packaging solutions that save space by stacking several chips on top of one another.
Whether a semiconductor company chooses to use an SoC design or use a 3D package depends on its business criteria. In general, everyone wants smaller, more compact devices, but vendors must take into account other considerations such as cost, performance, functionality, time-to-market, heat-dissipation and power consumption
For example SoCs typically have very high costs and long development times, but the related performance is usually better compared to similar devices that incorporate SIP, which relies on a wire bonder as its interconnect. SIP, on the other hand, is considered a cost effective and quick-to-market solution, and it is a viable option where performance of the device is not the key feature.
SiP has evolved as an alternative approach to System on Chip (SoC) because the technology provides advantages over SoC in many market segments. In particular SiP provides more integration flexibility, faster time to market, lower R&D cost, lower non-recurring engineering (NRE) cost, and lower production costs than SoC for many applications. However, SiP is not a replacement for high level, single chip, and silicon integration – instead it should be viewed as complementary to SoC.
Perhaps more importantly though, SIP architectures provide opportunities for vendors to use even more advanced off-chip interconnect schemes such as Through Silicon Vias (TSV). The TSV provide much shorter path lengths and lower resistance and inductance than bond wire structures for signal and power delivery.
In the TSV design, the chips are stacked on top of each other but instead of using wire bonding, each silicon via is etched in a manner that passes through all the layers. A material such as copper is then used to fill in the vias and function as interconnects, thus connecting all the chips into one.
TSV has the potential to facilitate cheaper development costs than that for SoC, while delivering better performance than SIP. TSV delivers advantages such as shortening the distance between circuitry without any limitations being set for how many dies can be stacked. Therefore, a TSV-made device with enhanced speed and performance is more suitable for smaller devices.
The technologies required for 3D-stacked SiP with TSV interconnections are wafer-thinning, drilling, filling of the conductive material as interconnections between wafers, and heat dissipation. TSV is mainly formed by the Bosch process, the principle of which is the repetition of oxidizing the silicon via wall and dry etching the bottom of the via.
The primary current development programs in the market for TSV involve "via first" and "via last" processes, depending on when the via is implemented in the production process.
Generally, via last applications are expected to be the first to market as the technical challenges are not as severe. The structures are larger, and thus easier to form while at the same time, offering a higher degree of connectivity to the outside world necessary in SiP (system-in-package) and other applications. This is generally a keen area of R&D interest to the packaging houses.
Easier does not mean easy though. The limiting factor in TSV technology is via filling. The aspect ratio for filling small diameter TSV structures is limited unless a very slow process is used. Fine pitch via filling is primarily done through copper plating. The filling of larger vias can be accomplished through many processes. The processes in use today for production filling of large vias include poly-Si, conductive paste and several others.
Under the via first program, vias are implemented on the wafer prior to any production process. Via first formation, however, is technically more challenging. The structures have a much higher aspect ratio – making the via formation difficult, from etching the via, to getting adequate isolation (to prevent parasitics), and then being able to metal seed and plate. These challenges will delay the adoption of via first relative to via last, but it is via first – due to its intrinsically higher I/O opportunity (and hence the opportunity to keep on Moore's law without necessarily achieving device shrinkage) – that many players in the industry see as the holy grail. It is the most attractive 3D IC application to the design houses, and thus a higher value add proposition to the IDMs. Via first will probably be implemented by foundries and IDMs but not by packaging houses.
However, TSV presents significant assembly challenges. Because 3D wafer stacking, based on through-silicon vias, requires etch, CVD and PVD processes in a "fitted" process to achieve reliable through wafer interconnections, the processes cannot be treated in isolation because the characteristics of one process affects the next in line.
This mean placement accuracy and, more importantly, the attachment method must be precise. The attachment will depend on the configuration of the die with the TSV – as in addressing concerns such as will they be stacked or placed on a substrate? The issues with TSV assembly, especially in SiP assembly are still not totally defined.
However a leading TSV consortium EMC-3D recently announced that it had developed a process and cost model for interconnect TSV structures. Rozalia Beica, program manager of EMC3D and TSV director at consortium-member Semitool, said that the via-first feature size of 5 microns in diameter by 30 microns deep was chosen because of the challenges these dimensions present for etch and deposition, as well as the increased interest and customer requests.
The integrated process includes litho and hard mask for the etch process, DRIE for the via creation, thermal and CVD liner and barrier, wet copper seed, copper electroplate fill, CMP and associated wafer cleans to complete the via. The wafers are then processed using standard CMOS technology and finally passed back to the TSV group for backside processing, including thinning, lithography, copper redistribution, solder bump, dicing and die-to-wafer-placement using temporary adhesive bonding before the final die attach step for a complete process flow.
Mark Scannell, microelectronics program manager of CEA-Leti in Grenoble, stated that the challenges are improving the integrated relationship of process steps such as etch, deposition, copper fill and CMP, as well as improving the speed and accuracy of the die-to-wafer placement during die attach. Many of the unit processes are well understood and characterized. The challenges now are to bring the technology to mass production in a cost effective package.
Dr. Yoon-Chul Sohn of Samsung SAIT said the next challenge is to now design an effective 3D structure for better electrical and thermal performance and determine its relationship with material defects, mechanical stress and electro-migration on these features."
The consortium also indicated that ownership for a 10,000 wafers per month capacity line is now achievable at less than US$190 per wafer. The EMC-3D cost model identifies the current complete cost of ownership to be US$189 for all the steps, and the model allows the consortium to identify the cost improvement programs needed to bring the price below US$145 per wafer.
Amid such market progress, industry players are building up strong expectations for TSV. According to Tong, TSV will be applied everywhere in the market. In addition to those players in the packaging and testing industry that have already devoted resources on TSV (via-last) development, he noted that many IDMs are introducing TSV in their front-end process (via-first) in an attempt to maximize space usage on a 2D space. TSV is now a battlefield that all industry players are eyeing, he added.
According to market research firm Yole Developpement , millions of 3D-TSV wafers will be shipped and the technology has the potential to impact as much as 25% of the memory business by 2015. Excluding memory devices, 3D-TSV wafers can account for more than 6% of the total semiconductor industry by 2015.
In order to fulfill customers' requirements in terms of cost and time-to-market schedule, ASE is aggressively developing into TSV technology, with the corresponding sales contribution expected to emerge in 2009, Tong said. ASE has its competitive edge in TSV development built on a complete supply chain support from substrate, packaging and testing. With production and development based on existing equipment, ASE will only have to procure some new equipment and then do an upgrade.
Evolution or revolution
One industry executive commented during SEMICON Taiwan 2008 that TSV could change everything in the semiconductor industry. Yole pointed out that whole semiconductor industry supply chain will be affected – from IDMs to fabless and CMOS foundries, and OSATs to substrate and circuit assembly players as well. Yole believe 3D integration with TSVs could accelerate consolidation in CMOS wafer fabs and shift the market even more toward a fabless foundry model.
Tong is optimistic and he highlighted the importance of close ties among semiconductor players from different segments in the supply chain (foundries, materials suppliers, equipment vendors, etc.). Tong also indicated that he anticipates that such stronger ties among industry players will be win-win situation for those involved.
These are bright times for packagers worldwide, Yole concurred. The research firm argues that a whole new infrastructure needs to be developed in the "mid-end" of the semiconductor industry supply chain. New technologies, equipments and advanced materials coming both from the front-end and the back-end worlds are being developed and will give rise to a new revival of the semiconductor packaging and circuit assembly industries.
Motivations for going 3-D
Yole indicated that the technology has already been successfully introduced into production for MEMS and CMOS image sensors. The motivation is all about achieving a smaller form factor with increased package densities, coupled with bandwidth, RF and power consumption performance improvements. Cost is definitively set to be the strongest motivation to develop 3D technologies in the long run, Yole pointed out.
Tang noted that demand for TSV has already surfaced from the memory and CMOS image sensor segments. It is expected that more demand should come from baseband IC, radio frequency (RF) IC and CPU in the future, he added
For CMOS image sensors, vias will be partially or completely filled, depending on via filling approach being developed – copper for partial filling, poly-silicon or tungsten for completely filled vias – Yole indicated. Yole expects the number of I/Os to expand to several hundred interconnects per chip with the trend being to stack the DSP chips under the image sensor chip itself.
MEMS will also benefit from 3D as it will be implemented to combine a MEMS chip with its ASIC while wireless SiPs will combine the heterogeneous layers – which can be built on different lithography nodes and using different material substrates e.g. Si, GaAs, SiGe, etc.
Yole did admit that there are several barriers to entry for full scale 3D IC integration, including test, 3D EDA design tools, thermal management and 300mm equipment availability.
Regarding test, issues are close to being resolved as many solutions are currently being developed and evaluated, including double-side probe stations – BIST with JTAG, interconnect redundancies, among others, Yole noted. However, as contact probe test technologies will tend to be increasingly limited as the density of via pads increase, they may not scale to future pad dimensions pitch shrinks, Yole explained.
Moreover, as one portion of the industry is going toward W2W configurations with thin wafers, new requirements are emerging for testing-without-damage at the wafer level to ensure electrical functionality of the TSV, RDL and bump pad structures prior to the stacking of each layer. As a consequence, a lot of companies are requesting contact-less testing technologies based on optical or wireless methods, Yole pointed out.
Technology and equipment are being developed for wafer surface inspection, open/short electrical testing and 3-D system level functionality validation.
However, the landscape is completely different regarding the availability of 3D EDA design and thermal management software tools. Yole believes it will be a real challenge for the industry to have such tools ready by 2011.
The availability for 300mm 3D-TSV equipment is just a question of time, though. The first 300mm tools clusters have been shipped this year for production pilot-lines, Yole said. The related equipment market for 3D-TSV manufacturing tools will rapidly expand and surpass US$1 billion by 2013, the research firm stated.
As for the 3D-TSV market for advanced materials, Yole forecasts it will break the US$1 billion level by 2015. |
