The new DDR3 SDRAM uses a copper interconnect process that is superior to aluminum in terms of transmission characteristics. By taking maximum advantage of these characteristics during the design phase new circuitry can be developed that enables even faster products that continue to need little power. As a result, the new product's ability to operate at an ultra low voltage of 1.2V can contribute to lower power consumption, which is especially important in the case of large-memory capacity extended-use server applications. Also, for high-end PCs geared to high-speed operations an operational speed of 2.5Gbps enables a significant system performance upgrade.
The new copper interconnect-based DDR3 SDRAM is intended for applications in the areas of servers and high-end PCs. Sample shipments are scheduled to begin by the end of August. Also, Elpida plans to use a process shrink to enable the new memory product to achieve even faster speeds and lower voltage.
elpida.com
Shrunken 65nm process is more competitive: Q&A with Kumi Higuchi, vice president of Elpida Memory
Printer friendly
Related stories
Comments
Email to a friend
Latest news
Josephine Lien, Taipei; Steve Shen, DIGITIMES [Thursday 9 October 2008]
Japan-based Elpida Memory has recently come out with a shrunken 65nm process for the production of DRAM chips, which the company claims will be able to compete effectively with the 50nm-class processes currently being developed by rivals in South Korea. Elpida vice president for investment and public relations, Kumi Higuchi, discussed the company's deployment plans for the shrunken 65nm node, as well as her view of the prospects for the DRAM industry in a recent interview with Digitimes.
Q: While your company has come out with a shrunken 65nm process, Samsung Electronics and Hynix Semiconductor are migrating to 50nm-class nodes. How does Elpida see its current competition in terms of process advancement?
A: Our 65nm shrunken process is able to deliver 20% more chips than a typical 65nm-node 12-inch wafer with just a simple upgrade to our existing equipment, and minimal additional capital expenditure.
In comparison, Samsung's 50nm process will be able to ramp up chip output over 25% per 12-inch wafer, whereas Hynix's 50nm process will deliver 21% more chips. However, migration to the 50nm process also requires addition investment in production equipment which could push up overall equipment costs by 20%. We believe this will make the 50nm-class processes less competitive compared to our shrunken 65nm process.
Q: Does that then imply Elpida is going to slow down its development and investment in the 50nm node?
A: Prospects for the DRAM industry are still uncertain and so we have decided to use our cash on hand cautiously. The shrunken 65nm process will become our main process node. We will not commit more investment in the 50nm process until there is an upturn in the market or when the market for DDR3 begins to gain momentum.
Q: How is your current distribution of production capacity among process nodes?
A: Our Hiroshima plant is currently focusing on 70nm production with a capacity of 120,000 wafers. But we have announced plans to cut output by 10% at the plant which will see us roll out 80,000 wafers using a 70nm process and about 30,000 wafers using a 65nm process. Production of 65nm parts will then gradually migrate to our shrunken process.
The ratio of 70nm process wafers will remain high because most of our clients from the handset and digital home appliances sectors continue to require this option. The 70nm process is still making money. Also PC clients are still in the process of validating our 65nm node with their products.
Q: What about production capacity at your joint venture with PSC, Rexchip?
A: Rexchip focuses on the production of DRAM chips for PC clients and so has to migrate to the 65nm node as soon as possible in order to reduce production costs. Rexchip currently has a capacity of 80,000 wafers a month and total production will be migrated into the 65nm node before the end of first-quarter 2009.
Q: What is your assessment of price trends in the DRAM chip market?
A: According to the market research company WTS, global DRAM output is expected to grow 90% on year in 2008. This has lead to an oversupply in the industry. We expect the market to remain weak, and will only begin to show an improvement in the beginning of second-quarter 2009. The effectiveness of production cuts initiated by us and PSC may begin to manifest starting November 2008, and this may help ease market conditions.
However, some DRAM vendors are now offering 1Gb DDR2 parts at around US$1 per unit on the spot market, which could push down contract quotes.
Q: What are your plans for capital expenditure as well as projected bit growth rates, for 2008 and 2009?
A: We are likely to post a 100% bit growth in 2008, but growth is expected to decline to below 50% in 2009. Bit growth for 2009 includes chips purchased from our production partner PSC and half the of output of Rexchip. Capex hit a high of 240 billion yen (US$2.35 billion) in 2007 due to the establishment of Rexchip. We will see our capex drop to a normal level of 120 billion yen in 2008 and 120 billion yen is also likely for 2009 unless we are required to ramp output for DDR3 in the coming year.
Q: Now that Micron Technology is likely to take over Qimonda, what will become of your technology cooperation agreement?
A: We have temporarily suspended our cooperation with Qimonda due to its financial difficulties. The talks between Micron and Qimonda have also made the issue more complicated. |
