SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 214.990.0%Dec 26 9:30 AM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: rzborusa who wrote (256931)11/6/2008 10:22:51 AM
From: neolibRead Replies (1) of 275872
 
Like it is probably mostly timing problems and the lack of delays, read distance, that require more precise timing, just my two cents.

Yes, I suspect it is mostly the details about drive strength and timing, but my question was "Is not most (all?) of that automated". If it is automated, what takes so long?

In reading up more on Fusion, I see that what I'm calling "some interface logic" does not quite describe things. They are doing a fair amount of architectural work to define how these cores are going to fit together in a more general manner and perhaps with an eye towards more core diversity in the future.

I was thinking more of just placing a CPU and GPU and connecting them on chip with HT, all the pieces of which they already have, other than the CPU and GPU are on difference processes.
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext